Abstract: A digital signal processing circuit including: a multiplier circuit; a plurality of multiplexers coupled to the multiplier circuit and controlled by a first opcode; and an arithmetic logic unit coupled to plurality of multiplexers and controlled by a second opcode.

Abstract: A physical floorplan for a digital signal processing (DSP) block including; an interconnect column having a plurality of programmable interconnect elements; a first DSP element having a plurality of first columns, a first output register column of the plurality of first columns positioned adjacent to the interconnect column; and a second DSP element, having a plurality of second columns a second output register column of the plurality of second columns positioned adjacent to the interconnect column.

Abstract: Methods of using one of a plurality of configuration bitstreams in an integrated circuit are disclosed. An exemplary method comprises analyzing the plurality of implementations of a design to determine initial variations in timing among the implementations; modifying the implementations to reduce the variations in timing among the implementations; and outputting a plurality of configuration bitstreams for the implementations having variations in timing that are reduced relative to the initial variations in timing. Another method comprises generating a plurality of implementations for the design; generating a cost function for the design based upon costs (e.g.

Abstract: A method of configuring a plurality of memory elements having selectable dimensions, the method comprising the steps of selecting a width of a data word to be output by a circuit having the plurality of memory elements; selecting a width for memory locations of the plurality of memory elements, the width for the memory location being less than the width of a data word; configuring the plurality of memory elements to have the selected width; and concatenating the outputs for the plurality of memory elements to generate a concatenated output comprising a data word. A circuit for configuring a plurality of memory elements having selectable dimensions is also disclosed.

Abstract: A circuit structure for determining a period of time during which a device was without power is disclosed. The circuit structure comprises a volatile memory storing known data and a test circuit coupled to the volatile memory, the test circuit determining an amount of incorrect data stored in the volatile memory after a period of time during which the device was without power. The amount of incorrect data is used to determine the period of time during which the device was without power. A method of controlling a device based on the amount of incorrect data stored in a volatile memory after the device was without power is also disclosed. For example, the device can be controlled by altering a start-up sequence of one or more elements of the device.

Abstract: A socket for an integrated circuit is disclosed. The socket comprises a main body portion having a plurality of holes extending between a top surface and a bottom surface; an overlay positioned adjacent to the main body portion and having a plurality of holes corresponding to the plurality of holes of the main body portion, wherein the overlay comprises a plurality of conductors between holes; and a plurality of contact elements positioned in predetermined holes of the main body portion. A method of providing a connection in a socket is also disclosed.

Abstract: An integrated circuit that includes a digital signal processing element (DSPE) having a first and a second register block coupled to a first arithmetic logic unit (ALU) circuit; a middle DSPE adjacent to the top DSPE having a third and a fourth register block coupled to a second ALU circuit, where the third register block is coupled to the first register block, and the fourth register block register block is coupled to the second register block; and a bottom DSPE adjacent to the middle DSPE having a fifth and a sixth register block coupled to a third ALU circuit, where the fifth register block is coupled to the third register block and the sixth register block register block is coupled to the fourth register block.

Abstract: A method of testing input signals coupled to a circuit for performing a predetermined function is disclosed. The method comprises coupling input signals to inputs of the circuit by way of programmable interconnects; controlling the paths of the input signals within the circuit from the inputs to an output of the circuit; maintaining the states of the input signals coupled to the inputs of the circuit and routed to the output of the circuit; and testing output signals of the circuit to determine whether the correct input signals were provided to the inputs of the circuit by way of the programmable interconnects. A device having programmable logic which enables testing of input signals is also disclosed.

Abstract: A circuit enabling the realignment of data is described. The circuit generally comprises an input multiplexer receiving a first plurality of input data bytes and a second plurality of input data bytes; a switching controller coupled to the input multiplexer and controlling the output of the data bytes from the input multiplexer; a delay register coupled to the input multiplexer and receiving predetermined bytes of the first plurality of input data bytes; and an output multiplexer coupled to the input multiplexer and the delay register. The output multiplexer receives the predetermined bytes of the first plurality of input data bytes and predetermined bytes of the second plurality of input data bytes.

Abstract: A contact pad in an integrated circuit is disclosed. The contact pad comprises a flat portion comprising a base of the contact pad; a plurality of projections extending from and substantially perpendicular to the flat portion; and a solder ball attached to the projections and the flat portion. A method of forming a contact pad is also disclosed.

Abstract: A method of suppressing noise in a circuit is disclosed. The method comprises providing a supply voltage to a first terminal of the circuit; providing a ground voltage to a second terminal of the circuit; providing a clock signal to the circuit; and actively decoupling noise from at least one of the first terminal and the second terminal of the circuit by actively decoupling noise synchronously with the clock signal. A circuit for suppressing noise in a circuit is also disclosed.

Abstract: Methods of enabling the validation of an integrated circuit adapted to receive one of a plurality of configuration bitstreams for a circuit design is disclosed. The method comprises analyzing a plurality of implementations for the circuit design; determining minimum timing constraints based upon all of the implementations for the circuit design; generating a representative implementation, based upon the plurality of implementations, which meets the determined minimum timing constraints for all of the implementations of the circuit design; and outputting the representative implementation.

Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises an integrated circuit die having a plurality of solder bumps; and a substrate comprising a first plurality of contact pads on a first surface and a second plurality of contact pads on a second surface. The plurality of solder bumps on the integrated circuit die is coupled to the first plurality of contact pads on the first surface of the substrate, wherein at least one edge of the substrate is formed after the integrated circuit die is attached to the substrate. According to one embodiment of the invention, the at least one edge of the substrate is formed after excess substrate material is detached at designated areas. According to another aspect of the invention, an assembly fixture is disclosed. An apparatus and method for assembling an integrated circuit package are also disclosed.

Abstract: A method of accessing a memory of a trellis decoder. The method comprises the steps of writing a first block of data associated with a trellis function to a first memory block; writing a second block of data associated with the trellis function to a second memory block; simultaneously writing a third block of data to a third memory block and reading the second block of data from the second memory block to generate training data; and simultaneously reading data to be decoded from the first memory block and writing a fourth block of data to the first memory block and generating training data associated with the third block of data. A circuit for accessing a memory of a trellis decoder is also described.

Abstract: An integrated circuit package has a substrate; a discrete capacitor coupled to a first surface of the substrate; an integrated circuit die coupled to the first surface of the substrate over the discrete capacitor; and a lid coupled to the substrate, the lid encapsulating the integrated circuit die and the discrete capacitor.

Abstract: A method of oversampling a signal in an integrated circuit is disclosed. The method comprises receiving a reference clock signal; generating at least one delayed clock signal, each having a different phase; receiving an input data signal; generating at least one delayed data signal based upon the input data signal; and generating a plurality of phase-shifted output signals, each phase-shifted output signal being based upon a different combination of a clock signal and a data signal. A circuit for oversampling a signal in an integrated circuit is also disclosed.

Abstract: A method of protecting a transistor formed on a die of an integrated circuit is disclosed. The method comprises forming an active region of the transistor on the die; forming a gate of the transistor over the active region; coupling a primary contact to the gate of the transistor; coupling a programmable element between the gate of the transistor and a protection element; and decoupling the protection element from the gate of the transistor by way of the programmable element. Circuits for protecting a transistor formed on a die of an integrated circuit are also disclosed.

Abstract: A circuit may be used for testing for faults in a programmable logic device. The circuit may include a clock generator coupled to receive a reference clock signal and generate a high speed clock signal; a circuit under test coupled to receive selected pulses of the high speed clock signal; and a programmable shift register coupled to receive a pulse width selection signal and generate an enable signal for selecting the pulses the high speed clock signal, wherein the pulse width of the enable signal is selected based upon the value of the pulse width selection signal. A method of testing for faults in a programmable logic device is also disclosed.

Abstract: A method of verifying configuration data to be loaded into a device having programmable logic is described. The method comprising the steps of validating a configuration bitstream to be loaded into the device having programmable logic; storing a validation indicator with the configuration bitstream in a non-volatile memory device; and configuring the programmable logic according to the configuration bitstream if the validation indicator indicates that valid data is stored in the non-volatile memory device. A system for verifying configuration data to be loaded into a device having programmable logic is also described.

Abstract: A method of adapting parameters for a predistortion circuit in an integrated circuit is disclosed. The method comprises receiving, at the predistortion circuit, an input signal to be amplified by a power amplifier; determining a value associated with an information tag for the input signal; applying parameters to the predistortion circuit based upon the determined value; receiving an output of the power amplifier at an input of the integrated circuit; comparing an output of the predistortion circuit with the output of the power amplifier; and generating updated parameters to be applied to the predistortion circuit. An integrated circuit having a circuit for adapting parameters for a predistortion circuit of the integrated circuit is also disclosed.