Abstract: A driver for a DC-to-DC converter that may utilize a flyback or buck-boost converter circuit. The driver includes a driver circuit and an interface circuit. The interface circuit has a sensor sensing an input voltage from a DC supply and generating a sensor signal to a driver selector. The driver selector compares the sensor signal to a comparison voltage to determine the type of converter circuit and then transmits a selector signal to a driver circuit where it is used to control one or more of the components of the driver circuit, such as the logic circuit which is used for driving the converter to regulate the converter output. The sensor includes a sense resistor along with a current-sense amplifier, which is adapted for connection to a high side or a low side of a power supply while still producing a substantially equivalent output voltage or sensor signal.

Abstract: A gate structure in a transistor and method for fabricating the structure are disclosed. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure.

Abstract: A data sorter includes a storage sorter that sorts a data set according to a defined criteria; and a query mechanism that receives intermediate sorted data values from the storage sorter and compares the intermediate sorted data values to a key value. The storage sorter includes a priority queue for sorting the data set. The priority queue has M processing elements. The query mechanism receives the intermediate sorted data values from the M processing elements. The query mechanism includes a plurality of comparison circuits, each of which is capable of detecting whether one of the intermediate sorted data values is equal to the key value or, if no match exists, extracting a minimal value greater than (or less than according to a defined criteria) the key value.

Abstract: A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is selectively applied. Conversely, if in standby no-read/no-write mode, then the second set of voltages is selectively applied. A low voltage in the second set of voltages is greater than a low voltage in the first set of voltages by a selected one of a plurality of low offset voltages, and a high voltage in the second set of voltages is less than a high voltage in the first set of voltages by a selected one of a plurality of high offset voltages. The offset voltages are provided by diode-based circuits that are selectively active. Selective activation is provided by either selectably blowable fuse elements or selectively activated switching elements.

Abstract: A USB device, integrated circuit, smart card and method are disclosed. A USB transceiver is connected to a data interface and operable at a respective low speed and full speed configuration. A processor as a USB device controller is operatively connected to the low speed USB transceiver and full speed USB transceiver and operable for transmitting a different device descriptor to a USB host for performing an enumeration depending on whether a low speed or high speed operation is chosen.

Abstract: A design method for an integrated circuit adds spare cells in a System-on-Chip to allow for Engineering Change Orders (ECOs) to be performed at a later stage in the design. This method can be used to provide a second version of the chip having minimal alterations performed in a short cycle time. The spare cells can be divided into combinational and sequential cells. There is an optimum spread of combinational cells in the design for post placement repairs of the chip with just metal layer changes. The method takes into account the drive strength of the spare cells as the main factor in their placement on the chip.

Abstract: A method includes receiving an activation signal at a semiconductor device and generating an output power signal at the semiconductor device in response to receiving the activation signal. The output power signal has a duty cycle. The method also includes providing the output power signal to a load. The output power signal provides power to the load. An amount of power provided to the load is based on the duty cycle of the output power signal. In addition, the method includes adjusting the duty cycle of the output power signal using at least one of a current limiter and a power limiter integrated in the semiconductor device.

Abstract: A system on chip (SoC) integrated circuit includes a plurality of computational blocks. A modular data transfer architecture interconnects the computational blocks for intra-chip communications. The computational blocks include an initiator block and a target block, with the initiator block originating a data communication having a global address associated with the target block. The modular data transfer architecture includes a first peripheral module having an initiator port connected to the initiator block to receive the data communication and a second peripheral module having a target port connected to the target block. A first port mapper within the first peripheral module maps the global address to a first peripheral module target port along a data path towards the second peripheral module. A second port mapper within the second peripheral module maps the global address to the target port connected to the target block.

Abstract: A subpixel interpolator includes an input memory capable of storing video information formed from full pixels. The subpixel interpolator also includes at least one interpolation unit capable of performing subpixel interpolation to generate half-pixels and quarter-pixels in parallel. Multiple half-pixels and multiple quarter-pixels are generated concurrently during the subpixel interpolation. In addition, the subpixel interpolator includes an output memory capable of storing at least some of the full pixels, half-pixels, and quarter-pixels. In some embodiments, the at least one interpolation unit includes a horizontal half-pixel interpolation unit, two vertical half-pixel interpolation units, and a quarter-pixel interpolation unit, all of which may operate in parallel. In particular embodiments, the interpolation units are formed from adders and shifters and do not include any multipliers.

Abstract: A switched capacitor regulator in accordance with the present invention comprises a DC voltage source, a plurality of switches, a pumping capacitor, and a load capacitor. The plurality of switches may comprise semiconductor switches implemented in an integrated circuit (IC). The plurality of switches is configured to operate the switched capacitor regulator to place the regulator into a first charging stage and, alternately, a second charging stage. The switching between the first stage and the second stage results in the pumping capacitor being charged in opposing directions, while the load capacitor is always being charged in the same direction. The load capacitor is thus being charged in both the first charging stage and the second charging stage.

Abstract: The CPU breaks a digital still image file down into multiple sub-picture files. Each sub-picture file is treated as an MPEG video frame and is used to construct an MPEG video stream. An MPEG processor then processes the MPEG video stream. The MPEG processor decodes the video stream and scales each sub-picture down to fit a monitor or television upon which the still image is to be displayed. Each scaled sub-picture is stored in a display buffer but is not displayed until the entire MPEG video stream is decoded.

Abstract: An energy-based pattern recognition algorithm receives the input frames of an audio signal and a test frame sequence and returns a best match in the audio signal to the given test frame sequence. The energy of each input frame is computed, and input frames for which the energy is within a predetermined degree of closeness to the local maximum energy within the test frame sequence are identified as probable matches. Probable matches are then eliminated if the respective probable match does not correspond to a local maximum within a respective neighborhood of adjacent frames. The difference between overall energy for frames neighboring the remaining probable matches and the test frame sequence is computed as a percentage, with the minimum percent deviation in energy from the test frame sequence being returned as the best pattern match. Local signal characteristic matching may be employed to refine matching.

Abstract: A motor driver includes an H-bridge having a first differential input, a second differential input, and a differential output; a sensing circuit coupled to the differential output of the H-bridge; a comparison and logic circuit coupled to the sensing circuit; a pair of pre-driver circuits coupled to the comparison and logic circuit for driving at least one of the differential inputs of the H-bridge; and a pair of level shifters coupled between the comparison and logic circuit and the sensing circuit. The pair of level shifters is used to assure that the VGS of a pair of serially coupled transistors in the sensing circuit do not change with temperature, motor current, or voltage, and each includes a transistor receiving a reference current. The pair of level shifters each further includes a serially coupled diode and zener diode for preventing current from flowing from the differential output of the H-bridge to the level-shifting transistor.

Abstract: A circuit includes a memory cell having a high voltage supply node and a low voltage supply node. Power multiplexing circuitry is included to selectively apply one of a first set of voltages and a second set of voltages to the high and low voltage supply nodes of the cell in dependence upon a current operational mode of the cell. If the cell is in active read or write mode, then the multiplexing circuitry selectively applies the first set of voltages to the high and low voltage supply nodes. Conversely, if the cell is in standby no-read or no-write mode, then the multiplexing circuitry selectively applies the second set of voltages to the high and low voltage supply nodes. The second set of voltages are offset from the first set of voltages. More particularly, a low voltage in the second set of voltages is higher than a low voltage in the first set of voltages, and wherein a high voltage in the second set of voltages is less than a high voltage in the first set of voltages.

Abstract: A method includes receiving image information representing at least one image. The image information defines multiple pixels in the at least one image. The method also includes identifying filter weights associated with the pixels. The filter weights are based on edge contents of at least a portion of the at least one image. In addition, the method includes filtering the image information using the identified filter weights.

Abstract: A method for estimating the speed of a mobile device in a network is provided that includes selecting a correlation length from a plurality of possible correlation lengths. A correlation result is generated based on the selected correlation length. A speed estimate is generated for the mobile device based on the correlation result.

Abstract: A pen fault check circuit for an ink jet printer that includes a comparator that further includes a pen signal input, and a switch array coupled to the pen signal input, where the switch array includes a high voltage diode. Also, a method of checking for faults in a pen of an ink jet printer that includes the steps of generating a pen signal from a first constant current source and a pulse line resistance from a pulse line of an ink jet nozzle, generating a reference signal from a second constant current source and an external resistance from a external resistor, where the first current source and the second current source generate equal currents, and comparing the pen signal and the reference signal to determine if the ink jet nozzle is in a fault state.

Abstract: The present disclosure provides an addressable light emitting diodes (LED) architecture that is able to control a plurality of LEDs individually. The present disclosure further provides a method of controlling the operation of at least one chain of serially connected LEDs.

Abstract: A disk-controller (110) that is within a disk memory system (100) initiates the auto-transfer of host-requested-data from cache memory (120) without the intervention of a microprocessor (130) that is within the disk memory system. The system performs auto-transfer, without the intervention of the microprocessor, even when the first block of host-requested-data (301) is not within cache memory (311). The system includes disk-controller circuitry (11) that determines when at least a portion of the host-requested-data is somewhere within cache memory.

Abstract: The cross-sectional area of a thin-film transistor (TFT) is decreased in order to minimize bitline to supply leakage of the TFT. This is accomplished by utilizing a spacer etch process to manufacture a TFT having a very narrow and thin channel in a controllable manner. The spacer dimensions of the TFT may be adjusted by simply modifying the thicknesses of the poly gate and the channel poly. The channel thickness is limited by the thickness of the deposited channel polysilicon which may be as thin as approximately 300 ? to 500 ?, and the channel width of the TFT corresponds to the height of the spacer etched along the polysilicon gate of the device which may be as small as approximately 0.15 to 0.25 ?m.