Abstract: The device includes: a tunnel insulating layer, a charge trap layer; a blocking insulating layer; and a gate electrode sequentially formed on a substrate. The charge trap layer includes: plural trap layers comprising a first material having a first band gap energy level; spaced apart nanodots, each nanodot being at least partially surrounded by at least one of the trap layers, wherein the nanodots comprise a second material having a second band gap energy level that is lower than the first band gap energy level; and an intermediate blocking layer comprising a third material having a third band gap energy level that is higher than the first band gap energy level, formed between at least two of the trap layers. This structure prevents loss of charges from the charge trap layer and improves charge storage capacity.

Abstract: A light-emitting element capable of increasing the amount of light emitted, a light-emitting device including the same, and a method of manufacturing the light-emitting element and the light-emitting device include a buffer layer having an uneven pattern formed thereon; a light-emitting structure including a first conductive pattern of a first conductivity type that is conformally formed along the buffer layer having the uneven pattern formed thereon, a light-emitting pattern that is conformally formed along the first conductive pattern, and a second conductive pattern of a second conductivity type that is formed on the light-emitting pattern; a first electrode electrically connected to the first conductive pattern; and a second electrode electrically connected to the second conductive pattern.

Abstract: Wafer structures and wafer bonding methods are provided. In some embodiments, a wafer bonding method includes providing a conductive wafer and a plurality of insulating wafers, the conductive wafer being larger than the insulating wafers; performing a pre-treatment operation on the conductive wafer, the insulating wafers, or both; and directly bonding the insulating wafers to the conductive wafer.

Abstract: Provided are a method of driving a liquid crystal panel using self-masking, a masking circuit for performing the method, and asymmetric latches. The method includes supplying power to the liquid crystal panel; receiving a horizontal start pulse signal instructing source lines of the liquid crystal panel to be driven, from a timing controller; generating a horizontal start masking signal by masking at least one pulse of the horizontal start pulse signal; and driving the source lines in response to the horizontal start masking signal. The horizontal start masking signal turns off the switches until signals output from the source driver, which correspond to image data of the liquid crystal panel, are supplied. Accordingly, it is possible to prevent unknown image data from being displayed on the liquid crystal display when the liquid crystal panel is powered on.

Abstract: In a method of estimating a self refresh period of a semiconductor memory device according to an exemplary embodiment, a plurality of internal address signals are reset in response to a refresh reset signal. The plurality of internal address signals are sequentially changed synchronously with an oscillation signal. A refresh completion signal is generated based on the plurality of internal address signals. The self refresh period is detected based on the refresh reset signal and the refresh completion signal.

Abstract: A method of forming fine patterns of a semiconductor device by using carbon (C)-containing films includes forming an etching target film on a substrate including first and second regions; forming a plurality of first C-containing film patterns on the etching target film in the first region; forming a buffer layer which covers top and side surfaces of the plurality of first C-containing film patterns; forming a second C-containing film; removing the second C-containing film in the second region; exposing the plurality of first C-containing film patterns by removing a portion of the buffer layer in the first and second regions; and etching the etching target film by using the plurality of first C-containing film patterns, and portions of the second C-containing film which remain in the first region, as an etching mask.

Abstract: A security circuit includes an electrical fuse read only memory (ROM) including a plurality of electrical fuse units. The electrical fuse units are arranged to correspond to bit values of an initial security key before the electrical fuse ROM is programmed.

Abstract: Systems and methods are provided for probing an occluded body lumen, including a flexible conduit insertable into the body lumen, at least one delivery waveguide and at least one collection waveguide integrated with the flexible conduit and arranged to deliver and collect radiation about a distal end of said flexible conduit, at least one radiation source connected to a transmission input of the at least one delivery waveguide, at least one optical detector connected to a transmission output of at least one collection waveguide, a spectrometer connected with the at least one optical detector, and constructed and arranged to scan radiation and perform spectroscopy, and a controller programmed to process data from said spectrometer and provide information for directing said flexible conduit through obstacles within the occluded body lumen.

Abstract: Provided are a light-emitting element, a light-emitting device including the same, and methods of fabricating the light-emitting element and the light-emitting device. The light-emitting element includes a substrate on which a dome pattern is formed and a light-emitting structure conformally formed on the dome pattern. The light-emitting structure includes a first conductive layer of a first conductivity type, a light-emitting layer, and a second conductive layer of a second conductivity type sequentially stacked on the substrate. The light-emitting element also includes a first electrode formed on the first conductive layer and a second electrode formed on the second conductive layer.

Abstract: An internal voltage generating circuit is provided. The internal voltage generating circuit of a semiconductor device includes a control signal generating circuit for generating a control signal according to a number of data bits, a comparator for comparing a reference voltage to an internal voltage to generate a driving signal when the control signal is inactivated, a driving signal control circuit for inactivating the driving signal when the control signal is activated, and an internal voltage driving circuit for receiving an external power voltage and generating the internal voltage in response to the driving signal. Therefore, an internal voltage can be turned to a reference voltage level or to an external power voltage level according to the number of data input and/or output bits of a semiconductor device, and even when the number of data input and/or output bits is increased, a data access speed can be improved.

Abstract: A semiconductor device can include a semiconductor chip, a protective layer pattern, an under bump metallurgy (UBM) layer, and conductive bumps. The semiconductor chip can include a pad and a guard ring. The protective layer pattern can be formed on the semiconductor chip to expose the pad and the guard ring. The UBM layer can be formed on the protective layer and can directly make contact with the pad and the guard ring. The conductive bumps can be formed on a portion of the UBM layer on the pad. Thus, the UBM layer and the guard ring can directly make contact with each other, so that a uniform current can be provided to the UBM layer on the pad regardless of a thick difference of different portions of the UBM layer.

Abstract: Provided is a method of manufacturing a semiconductor device having a capacitor under bit line (CUB) structure capable of increasing a gap between a bit line in a cell area and an upper plate of a capacitor, reducing coupling capacitance therebetween, and forming deep contacts in a logic area. A capacitor including a lower electrode, a dielectric material layer, and an upper electrode is formed in an opening of a first insulating layer for exposing a first part of a semiconductor substrate in a cell area. A second insulating layer is formed on the first insulating layer. The first and second insulating layers are etched. First and second contact plugs are formed in first and second contact holes for exposing second and third parts in the cell area and the logic area. A third insulating layer including first through third conductive studs is formed on the second insulating layer.

Abstract: In a method of programming a non-volatile memory device, a first voltage is applied to a selected word line corresponding to a selected memory cell transistor of a selected transistor string to be programmed; a second voltage is applied to a neighboring word line neighboring the selected word line and corresponding to a neighboring transistor of the selected transistor string, wherein the first voltage is greater than the second voltage, the application of the first and second voltages to the selected and neighboring word lines respectively causing electrons to be generated by an electric field formed between the neighboring transistor and the selected memory cell transistor, the electrons accelerating toward the selected memory cell transistor and injecting into a charge storage layer of the selected memory cell transistor; wherein the neighboring transistor is positioned between the selected memory cell transistor and one of a ground select transistor and a string select transistor, and the first voltage is

Abstract: A method of fabricating a light-emitting element, in which less stress is applied to the light-emitting element, includes: forming element isolation patterns on a substrate; forming a buffer layer on an entire surface of the substrate to directly contact the surface of the substrate and the element isolation patterns and forming light-emitting structure layers on the buffer layer; forming element isolation trenches, which overlap at least part of the element isolation patterns, respectively, buffer layer patterns and light-emitting structures which are separated from each other by the element isolation trenches, respectively, by etching the buffer layer and the light-emitting structure layers; injecting a lift-off solution into the element isolation trenches to remove the element isolation patterns; and removing the substrate.

Abstract: In a program method for a multi-level phase change memory device, multi-level data to be programmed in a selected memory cell is received, and a program signal is applied to the selected memory cell according to the received multi-level data. Herein, a rising time of the program signal is set to be longer than a falling time of the program signal.

Abstract: Various aspects of the present invention include a database interaction system and method comprising: a display, a set of user input devices, and a database comprising a data set including a plurality of fields and associated field values; a graph model configured to define a plurality of nodes and states, each node representing a field from the plurality of fields; a graph-to-data mapper configured to map the field values to states contained in the nodes of the graph model; and a graphical interface module configured to generate for display one or more nodes from the plurality of nodes, wherein a display of a node includes a graphical representation of field values associated with a specific field represented by the displayed node and states contained therein.

Abstract: In a semiconductor device, and a method of manufacturing thereof, the device includes a substrate of single-crystal semiconductor material extending in a horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of single-crystal semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality to of gate patterns, a gate insulating layer being between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.

Abstract: A system on a chip (SoC) device verification system comprises: an SoC device model including one or more IPs and a memory controller; an external IP verification model receiving an instruction from the SoC device model and verifying operation of the one or more IPs included in the SoC device model; and a bus select model selecting one of the external IP verification model and an external device in response to a memory control signal received from the memory controller of the SoC device model.