Abstract: Provided is a semiconductor package and method of manufacturing same. The method includes: forming a plurality of semiconductor chips which have the same pattern direction on a semiconductor substrate, each of which includes a memory cell region, a peripheral region and a pad region, and in each of which the pad region is disposed in an edge region; separating the semiconductor chips, which are formed on the semiconductor substrate, from one another; and disposing semiconductor chips, which are selected from the separated semiconductor chips, on a package substrate by changing the pattern directions of the selected semiconductor chips and arranging pad regions of the selected semiconductor chips in a center region of the package substrate.

Abstract: A fluid dispensing system includes a dispensing pump for delivering the fluid material to a substrate. The fluid dispensing system further includes a vacuum unit that draws a vacuum on the feed tube for removing gas impurities from the fluid material.

Abstract: A memory device comprises a plurality of memory cells, each memory cell comprising a memory cell material that has an initial resistance that is determined in response to an applied programming current in a programming operation, the resistance of the memory cell varying from the initial resistance over a time period following the programming operation, and each memory cell being connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a read operation. A modification circuit modifies the resistance of a memory cell of the plurality of memory cells selected for a read operation to return its resistance to near the initial resistance prior to a read operation of the memory cell.

Abstract: Provided is a method of forming a semiconductor memory cell in which in order to store two bits or more data in a memory cell, three or more bottom electrode contacts (BECs) and phase-change materials (GST) have a parallel structure on a single contact plug (CP) and set resistances are changed depending on thicknesses (S), lengths (L) or resistivities (?) of the three or more bottom electrode contacts, so that a reset resistance and three different set resistances enable data other than in set and reset states to be stored. Also, a method of forming a memory cell in which three or more phase-change materials (GST) have a parallel structure on a single bottom electrode contact, and the phase-change materials have different set resistances depending on composition ratio or type, so that four or more different resistances can be implemented is provided.

Abstract: In a method of detecting a defect on an object, a preliminary reference image can be obtained from a plurality of comparison regions defined on the object. The preliminary reference image is divided into reference zones by a similar brightness. Each of the reference zones is provided with substantially the same gray level, respectively, to obtain a reference image. Whether a defect exists in an inspection region in the comparison regions is determined using the reference image. Thus, defects in the inspection regions having different brightnesses can be detected using the properly obtained reference image.

Abstract: Provided are a method of fabricating a light-emitting apparatus with improved light extraction efficiency and a light-emitting apparatus fabricated using the method. The method includes: preparing a monocrystalline substrate; forming an intermediate structure on the substrate, the intermediate structure comprising a light-emitting structure which comprises a first conductive pattern of a first conductivity type, a light-emitting pattern, and a second conductive pattern of a second conductivity type stacked sequentially, a first electrode which is electrically connected to the first conductive pattern, and a second electrode which is electrically connected to the second conductive pattern; forming a polycrystalline region, which extends in a horizontal direction, by irradiating a laser beam to the substrate in the horizontal direction such that the laser beam is focused on a beam-focusing point within the substrate; and cutting the substrate in the horizontal direction along the polycrystalline region.

Abstract: A light-emitting element capable of increasing the amount of light emitted, a light-emitting device including the same, and a method of manufacturing the light-emitting element and the light-emitting device include a buffer layer having an uneven pattern formed thereon; a light-emitting structure including a first conductive pattern of a first conductivity type that is conformally formed along the buffer layer having the uneven pattern formed thereon, a light-emitting pattern that is conformally formed along the first conductive pattern, and a second conductive pattern of a second conductivity type that is formed on the light-emitting pattern; a first electrode electrically connected to the first conductive pattern; and a second electrode electrically connected to the second conductive pattern.

Abstract: In a semiconductor memory device and method, resistive-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices comprising a resistive-change memory. Each resistive-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of resistive-change memory cell groups storing data while being connected to the local bit lines, respectively.

Abstract: A semiconductor memory device includes a plurality of memory banks; a plurality of temperature sensing circuits, and a shared control circuit. The temperature sensing circuits correspond to the memory banks and each is disposed in the vicinity of a corresponding memory bank. The shared control circuit is connected to the plurality of temperature sensing circuits and a plurality of refresh circuits for refreshing the plurality of memory banks, performs calibration on the plurality of temperature sensing circuits, performs digital processing on signals for separately controlling refresh intervals for the plurality of memory banks, and transmits the processed signals to the plurality of refresh circuits. Therefore, the refresh intervals for individual channels or banks are separately or selectively controlled. Further, since the plurality of temperature sensing circuits are connected to the shared temperature control circuit, the occupied area of the circuits in a chip is reduced or minimized.

Abstract: There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures.

Abstract: A test board includes a socket, a mounting test circuit, and a relay. An analog core embedded application processor is installed into the socket. The mounting test circuit has a same configuration as an environment where the analog core embedded application processor is actually used. The relay disconnects the mounting test circuit from the socket in response to a first control signal when a vector test is performed on the analog core embedded application processor, and that connects the mounting test circuit to the socket in response to a second control signal when a mounting set test is performed on the analog core embedded application processor.

Abstract: A method of programming a nonvolatile memory device according to the present invention includes precharging bit lines according to data loaded in page buffers; electrically connecting the precharged bit lines to channels corresponding to the bit lines, respectively, to charge the channels; and applying a word line voltage for a program after charging the channels. A channel voltage boosting of each of the channels is determined according to data loaded in adjacent page buffers.

Abstract: The present invention is directed to a vertical-type luminous device and high through-put methods of manufacturing the luminous device. These luminous devices can be utilized in a variety of luminous packages, which can be placed in luminous systems. The luminous devices are designed to maximize light emitting efficiency and/or thermal dissipation. Other improvements include an embedded zener diode to protect against harmful reverse bias voltages.

Abstract: An electrostatic discharge (ESD) protection element includes a first diode, a second diode, and a poly resistor. The first diode is connected between a first voltage and an input/output (I/O) pad. The second diode is connected between the I/O pad and a second voltage. The poly resistor is formed on the second diode.

Abstract: In semiconductor devices, and methods of formation thereof, both planar-type memory devices and vertically oriented thin body devices are formed on a common semiconductor layer. In a memory device, for example, it is desirable to have planar-type transistors in a peripheral region of the device, and vertically oriented thin body transistor devices in a cell region of the device. In this manner, the advantageous characteristics of each type of device can be applied to appropriate functions of the memory device.

Abstract: A multi-plane scanner support system includes a bracket and a mirror block. The bracket is configured to be secured in a fixed orientation with respect to a scanner. And the mirror block is arranged to receive a scanning signal from the scanner and to reflect the scanning signal into a plurality of directions to create multiple scanning planes. The scanner can be a laser scanner. The scanner and multi-plane scanner support system can be attached to a material transport vehicle, for example, to provide safety functions. The vehicle can be manned or unmanned.

Abstract: A recessed channel transistor includes an isolation layer provided in a semiconductor substrate to define an active region. A trench is provided in the semiconductor substrate to extend across the active region. A gate insulation layer covers a sidewall and a bottom face of the trench and an upper face of the semiconductor substrate adjacent to an upper edge of the trench, wherein a portion of the gate insulation layer on the upper surface of the semiconductor substrate adjacent to the upper edge of the trench and on the sidewall of the trench extending to a first distance downwardly from the upper edge of the trench has a thickness greater than that of a portion of the gate insulation layer on the remaining sidewall and the bottom face of the trench. A gate electrode fills up the trench having the gate insulation layer formed therein.

Abstract: A chemically doped boron coating is applied by chemical vapor deposition to a silicon carbide fiber and the coated fiber then is exposed to magnesium vapor to convert the doped boron to doped magnesium diboride and a resultant superconductor.

Abstract: A semiconductor memory device includes a refresh control circuit and a memory cell array. The refresh control circuit generates an internal auto refresh control signal based on a chip select signal and an external self refresh control signal. The memory cell array is refreshed in response to the internal auto refresh control signal. Because the semiconductor memory device internally generates the internal auto refresh control signal performing auto refresh operations, the semiconductor memory device may not be required to transmit to external devices for performing the auto refresh operations, and thus pins or pads for transmitting signals may be reduced and operation time may become faster.