Abstract: A voltage level shifter circuit, comprising diodes to provide a voltage buffer to reduce output voltage swings, and edge detection circuits to momentarily turn on pull-up pMOSFETs so as to speed up the voltage level shifting at input signal transitions and to mitigate static power dissipation. Other embodiments are described and claimed.

Abstract: A disc catching device for catching a thrown disc, having a canopy structure, a basket structure, an assembly coupled to the canopy structure and the basket structure, and a pole to which the canopy structure and the basket structure may be attached. The assembly may engage a thrown disc, and for some embodiments, may comprise chains. When the disc catching device is deployed in its upright position for the sport of disc golf, the assembly hangs from the canopy structure, and is coupled to a ring that surrounds the pole. The basket structure comprises a set of basket arms, and when the disc catching device is deployed upright, the ring hangs below the set of basket arms. For some embodiments, the canopy structure and the basket structure may be foldable, like an umbrella. For some embodiments, the basket arms may be basket support arms, where each basket support arm supports a basket arm. Other embodiments are described and claimed.

Abstract: For isochronous data steams processed by a computer system, for example high definition audio streams, embodiments keep track of the free space available in the input and output buffers for the data streams. The available free space in the buffers determines whether various low power entry and exit thresholds are met or not. If all low power entry thresholds are met, then various circuits such as clocks, phase locked loops, and direct media interface links, may be put into a low power state, and the data stream controller enters an idle window so that memory requests are not serviced. During this time, system DRAM may begin refresh. Once the low power state has been entered into, if any exit threshold is met, then the low power state is ended. Other embodiments are described and claimed.

Abstract: A circuit to synchronize the phase of a distributed clock signal to a received clock signal. Embodiments include a control loop comprising a phase interpolator, a clock distribution network, and a data receiver. The clock distribution network provides a sampling clock signal to clock the data receiver. The data receiver receives as its input the received clock signal. Control logic maps a subset of the output samples to a value, and this value is added to the phase introduced by the phase interpolator to provide an updated phase. Embodiments include a second phase interpolator and a second distribution network to clock a second data receiver, where the second data receiver receives the data. The control logic adjusts the second phase interpolator in the same way that it adjusts the phase interpolator. The two data receivers are matched to each other, and the two clock distribution networks are matched to each other. Other embodiments are described and claimed.

Abstract: Materials suitable for medical and dental implants with magnetic susceptibility matched to surrounding environment to reduce artifacts in nuclear magnetic resonance imaging. Paramagnetic and diamagnetic materials may be added to ceramics and polymer resins to adjust magnetic susceptibility. Other embodiments are described and claimed.

Abstract: Metallic glass alloys of palladium, copper, cobalt, and phosphorus, that are bulk-solidifying having an amorphous structure. Other embodiments are described and claimed.

Abstract: An integrated circuit with reduced pad capacitance, having a trench formed in the silicon substrate below the pad to reduce the pad capacitance. In another embodiment, an encapsulated air cavity is formed underneath the pad.

Abstract: A phasemeter for estimating the phase of a signal. For multi-tone signals, multiple phase estimates may be provided. An embodiment includes components operating in the digital domain, where a sampled input signal is multiplied by cosine and sine terms to provide estimates of the inphase and quadrature components. The quadrature component provides an error signal that is provided to a feedback loop, the feedback loop providing a model phase that tends to track the phase of a tone in the input signal. The cosine and sine terms are generated from the model phase. The inphase and quadrature components are used to form a residual phase, which is added to the model phase to provide an estimate of the phase of the input signal. Other embodiments are described and claimed.

Abstract: A phase locked loop with a voltage controlled oscillator, where the voltage controlled oscillator includes a feedback loop and delay cells connected in a ring. Each delay cell has a biased pMOSFET to provide pull-up current and a biased nMOSFET to provide pull-down current. For each delay cell, the gate of the biased nMOSFET is biased by the control voltage provided by the phase locked loop, and the gate of the biased pMOSFET is biased at a bias voltage provided by the feedback loop. The biasing of the pMOSFETs is adjusted so that the pull-up and pull-down currents for each delay cell are matched, thereby providing a 50% duty cycle and good jitter performance over process, supply voltage variations, and temperature variations. Because only the feedback loop has non-zero static current, low power is expected. Other embodiments are described and claimed.

Abstract: A clock receiver architecture for source synchronous digital data communication, the receiver including a forwarded clock amplifier to provide the received forwarded clock signal to a plurality of delay locked loops. Each delay locked loops provides to one or more phase interpolators a set of clock signals generated from the received forwarded clock, where the relative phases of the set of clock signals are uniformly spaced. Phase interpolators interpolate between two adjacent (with respect to phase) clock signals so as to provide a clock signal to sample received data at the center of the data eye. In some embodiments, an on-die voltage regulator provides a regulated supply voltage to the delay locked loops and phase interpolators.

Abstract: A switched-capacitor circuit that may be used for equalization, but configurable for voltage margining. The switched-capacitor circuit cancels the offset voltage inherent in an amplifier and sets the common mode of an input signal at half the rail voltage. Two capacitors level shift an input signal before being applied to the two input ports of an amplifier. When used for voltage margining, the input voltage swing is reduced at the input ports of the amplifier by connecting a digital-to-analog controlled voltage source to the two capacitors.

Abstract: A voltage-controlled oscillator (VCO) of ring-connected stages, where each stage in the VCO has a first set of differential inverters biased by variable bias voltages, and a second set of differential inverters biased by fixed bias voltages. The differential inverters in each stage are connected in parallel with each other. Each set of differential inverters in a stage may contain only one differential inverter. The variable bias voltages are provided by charge pumps and associated circuits as used in well-known self-biasing schemes for phase locked loops. The fixed bias voltages are provided by a biasing circuit, matched to the circuits associated with the charge pumps, but where a fixed control voltage is applied to provide the fixed bias voltages.

Abstract: A voltage regulator comprising two feedback loops for regulating a load voltage, where the first feedback loop comprises a pass transistor to source current to the load, and the second feedback loop comprises a shunt transistor to shunt current from the pass transistor to ground. The use of two feedback loops allows the design of a voltage regulator in which it small-signal impedance, as seen by a power rail, has a phase not less than ?90 degrees. This mitigates interactions between the power rail and the voltage regulator that may lead to oscillations, without the need for a relatively large de-coupling capacitor. Other embodiments are described and claimed.

Abstract: An adaptive tuning circuit to maximize the output signal amplitude of a band-pass amplifier, comprising a control circuit to tune the peak frequency of the amplifier by monitoring the change in the output signal amplitude over two successive time sampling intervals. In some embodiments, the control circuit comprises an envelope detector and a switched capacitor circuit to provide voltages indicative of the difference in the output signal amplitude over two successive time intervals. Other embodiments are described and claimed.

Abstract: Embodiments utilize analog sub-threshold circuits to perform Boolean logic and soft-gate logic. These analog circuits may be grouped into configurable logic blocks that are locally asynchronous, but block-level synchronous. The Boolean logic, or function, performed by these blocks may be configured by programming bits. Other embodiments are described and claimed.

Abstract: A circuit to divide down the frequency of a clock signal, where embodiment circuits comprise a set-reset flip-flop feeding its output to a shift register, and combinational logic to provide feedback from the shift register to the set input port, reset input port, or both set and reset input ports of the set-reset flip-flop. The set-reset flip-flop and shift register are clocked by the clock signal. The output signal of the circuit may be taken at any output port of the shift register or the set-reset flip-flop. In one embodiment, the state of the shift register is represented by the set of Boolean values Q<i>, i=1, 2, . . . , N?1, and the combinational logic provides to the set input port of the set-reset flip-flop the Boolean value {Q#<M?1><Q#<M?2>. . .

Abstract: According to an embodiment of the present invention, a capacitor comprising field effect transistors and a bias transistor.

Abstract: A three-stage transimpedance amplifier, where the first stage is a shunt-shunt feedback amplifier, the second stage is a simple voltage amplifier, and the third stage is a shunt-shunt feedback amplifier. The third stage comprises a pMOSFET serially connected with a nMOSFET, where their gates are connected together and to the output port of the second stage, and comprises a feedback pMOSFET or resistor to provide negative feedback from the drains of the pMOSFET and nMOSFET to the output port of the second stage.

Abstract: A word-based interface between a MAC and a PHY, allowing for variable pin counts, variable PHY and MAC data speeds, and variable numbers of connected PHYs. The word-based interface allows for the PHY to provide PHY-to-MAC words to the MAC, and for the MAC to provided MAC-to-PHY words to the PHY, where the PHY-to-MAC words are synchronized with the MAC-to-PHY words. Data and commands are provided in fields of the words, and may be time multiplexed over the interface. Circuits within the MAC and PHY allow for the MAC to detect if a PHY is present, the number of active pins, and the number of PHYs connected. The reset and synchronization signals are integrated into a single reset/sync signal. Identification data is exchanged between the MAC and PHY so that the proper device driver for the PHY may be loaded independently of the BIOS.

Abstract: An active cascode differential latch for providing a logic output signal indicative of whether or not a first current is greater than a second current. The first and second currents are fed into two input ports of the active cascode differential latch. The active cascode differential latch has a relatively small input impedance, and has utility for comparators and discrete-time analog filters, to name just a few, particularly when used in high bandwidth and low voltage applications.