Abstract: A computer architecture to process move instructions by allowing multiple mappings between logical registers and the same physical register. In one embodiment, a counter is associated with each physical register to indicate when the physical register is free. A register-to-register move instruction is processed by mapping the logical destination register of the move instruction to the same physical register to which the logical source register of the move instruction is mapped. An immediate-to-register move instruction is processed by mapping the logical destination register of the move instruction to a physical register storing the immediate.

Abstract: Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

Abstract: A differential envelope detector for detecting the envelope of a received differential signal. The received differential signal comprises first and second received voltages, and the differential envelope detector provides a differential output voltage comprising first and second output voltages, where the difference of the first and second output voltages is indicative of the envelope of the difference of the first and second received voltages. For full-wave rectification, the first received voltage is coupled to the non-inverting input port of a first differential amplifier and the inverting input port of a second differential amplifier, and the second received voltage is coupled to the inverting input port of the first differential amplifier and the non-inverting input port of the second differential amplifier. The output ports of the differential amplifiers are coupled to their input ports to provide negative feedback.

Abstract: A low output capacitance, current mode digital-to-analog converter. A low output capacitance is achieved by the use of a current mirror coupled to a plurality of digitally controlled current sources.

Abstract: A differential-input, differential-output CMOS amplifier having a first differential pair with a first transistor folded with a first cascode transistor, and a second differential pair with a first transistor folded with a second cascode transistor, and having a first auxiliary amplifier to provide negative feedback to the first and second cascode transistors to boost amplifier gain, where the first and second cascode transistors have gates at the same potential. The first differential pair has a second transistor folded with a third cascode transistor, and the second differential pair has a second transistor folded with a fourth cascode transistor, where a second auxiliary amplifier provides negative feedback to the third and fourth cascode transistors to boost amplifier gain, where the third and fourth cascode transistors have gates at the same potential.

Abstract: Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

Abstract: Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

Abstract: A reference buffer circuit having a first reference voltage circuit to provide a first reference voltage at a first port to sink a first current at the first port; a second reference voltage circuit to provide a second reference voltage at a second port to sink a second current at the second port; and a current source circuit to source a source current at an output port, where the output port is connected to the second port. In one application, the first and second ports are connected to a resistor ladder network of a flash analog-to-digital converter.

Abstract: A processor architecture for providing many-to-one mappings between logical registers and physical registers, so that more than one logical register may map to the same physical register. Each physical register has an associated counter to indicate whether the physical register is free. A counter is incremented each time a mapping is made to its associated physical register, and is decremented when that mapping is no longer needed. If a logical register named in a decoded instruction is predicted to have the same value as a value stored in a physical register, then the logical register is mapped to the physical register.

Abstract: Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

Abstract: A boosted high gain, very wide common mode range, self-biased operational amplifier comprising complementary differential transistor pairs biased by biasing transistors and current mirrors, and comprising two amplifiers, each connected to bias an output cascode transistor so as to provide a very high amplifier output impedance, wherein the biasing transistors and current mirrors are all self-biased via negative feedback.

Abstract: A double data rate dynamic logic gate in which an evaluation phase is performed for each phase of a clock signal. In one embodiment, an nMOSFET pull-down logic unit is clocked by two nMOSFETs switched in complementary fashion, and dynamic latches provide the output signals. In another embodiment, two nMOSFET pull-down logic units are employed, each clocked by an nMOSFET in complementary fashion, and a static logic unit provides the output signals.

Abstract: A low voltage swing priority encoder comprising pass cells to provide differential voltages indicative of the leading one of a binary tuple. A tree structure with bypass paths allows for the minimization of the number of pass cells in a signal propagation path so as to reduce signal delay. The pass cells are responsive to control voltages indicative of various Boolean functions of the binary tuple, and a pulse voltage signal is applied to the pass cells. In response to the control voltages and the pulse voltage signal, the pass cells provide differential voltages so that voltage swing of the differential voltages are kept below the supply voltage to reduce dynamic power dissipation. Sense amplifiers sense the differential voltages to provide the final logic level indicative of the leading one of the binary tuple.

Abstract: A microprocessor for providing an extended linear address of more than 32 bits. The extended linear address may be provided by concatenating a linear address with a segment selector extension, or by concatenating the values from two registers. Hierarchical translation of a linear address to a physical address is performed in which the number of levels in the hierarchy depends upon whether the linear address is an extended linear address.

Abstract: A calibration apparatus for calibrating a color imager, the calibration apparatus comprising an integrating sphere having at least one port, at least one light emitting diode, and an optical baffle so that light provided by the at least one light emitting diode is reflected upon the inner surface of the integrating sphere before exiting the at least one port.

Abstract: A high gain, very wide common mode range, self-biased operational amplifier comprising complementary differential transistor pairs biased by biasing transistors and current mirrors, and further comprising cascode transistors to provide a high amplifier output impedance, wherein the biasing transistors, current mirrors, and cascode transistors are all self-biased via negative feedback.

Abstract: A driver to drive a bus with a pullup and a pulldown transistor according to a data signal during a drive phase and to charge or discharge the bus to intermediate voltage levels during a precondition phase using the pullup and pulldown transistors, the driver comprising a buffer and latch to latch the bus voltage at the end of a drive phase; a precondition circuit responsive to the latch to switch ON a pullup transistor at the beginning of a precondition phase when the bus voltage was LOW in the previous drive phase so as to charge the bus voltage to a first voltage less than a supply voltage, and to switch ON a pulldown transistor at the beginning of the precondition phase when the bus voltage was HIGH in the previous drive phase so as to discharge the bus voltage to a second voltage above ground.

Abstract: A sense amplifier comprising first and second CMOS inverters, an pMOS current mirror, a nMOS current mirror, a source pMOSFET to source current, and a sink nMOSFET to sink current. The gate voltage of the first CMOS inverter is the input voltage and the gate voltage of the second CMOS inverter is at the reference voltage. The output voltage is at the drains of the first CMOS inverter. The pMOS and nMOS current mirrors provide active loads to the first and second CMOS inverters. The sense amplifier is self-biasing by connecting the gate of the source pMOSFET to the gates of the pMOS current mirror and by connecting the gate of the sink nMOSFET to the gates of the nMOS current mirror.

Abstract: A CMOS input/output driver having constant output impedance, the driver comprising a drive pMOSFET and a drive nMOSFET for driving an output node HIGH and LOW, an pMOSFET having a drain coupled to the output node and switchable so that its gate is coupled to the output node when the drive pMOSFET is driving the output node HIGH, and an nMOSFET having a drain coupled to the output node and switchable so that its gate is coupled to the output node when the drive nMOSFET is driving the output node LOW. The betas of the drive pMOSFET, the drive nMOSFET, the pMOSFET, and the nMOSFET are matched so that the output impedance of the drive is approximately independent of the output node voltage.

Abstract: A processor architecture with an instruction set having a predict instruction, the predict instruction providing static prediction information and a statically predicted target address to the processor for a branch instruction. The processor decodes a predict instruction to obtain an associated pair of addresses comprising a predicted target address and a referenced instruction address, and fetches a predicted target instruction having an instruction address matching the predicted target address when a fetched and decoded branch instruction has an instruction address matching the referenced instruction address.