Abstract: A high voltage drive output buffer for low voltage integrated circuits comprising a pullup pFET; a driver pFET having a source connected to the drain of the pullup pFET, and having a gate connected to a biasing circuit; a driver nFET having a drain connected to the drain of the driver pFET, and having a gate connected so as to be biased; and a pulldown nFET having a drain connected to the source of the driver nFET; wherein the pullup pFET and pulldown nFET are coupled to switch in complementary fashion in response to an input voltage; and wherein the biasing circuit comprises an nFET having a drain connected to the gate of the driver pFET and coupled to the input node so as to switch ON for a transitory period when the pullup pFET switches from OFF to ON.

Abstract: A switching DC-to-DC converter comprising a controller to regulate a load voltage according to a set-point and a sample-and-hold circuit, the sample-and-hold circuit coupled to the controller to decrease the set-point of the controller if an average of current flowing through the inductor increases.

Abstract: A half latch for latching a voltage at a domino gate output with reduced crossbar current duty cycle, comprising a CMOS inverter with input connected to the domino gate output, a first pMOSFET having a gate and drain connected to ground and having a source coupled to the source of the nMOSFET of the CMOS inverter to prevent the source voltage of the nMOSFET from approaching ground, and a second pMOSFET having a gate connected to the output of the CMOS inverter and having a drain connected to the input of the CMOS inverter.

Abstract: A broken stack domino priority encoder to provide a set of voltages to uniquely identify the position of a leading one or leading zero in a binary word, the domino priority encoder comprising a by-pass stack of nMOSFETs and a broken stack of nMOSFETs to discharge various nodes. The stack depth of nMOSFETs between each node and ground is minimized in order to maximize switching speed of the priority encoder.

Abstract: A method for BIOS code for detecting and grouping memory devices connected to one or more memory channels, comprising reading characteristics of a memory device and if the characteristics have not been previously read, then programming device ID and group ID registers based upon a device counter and a group counter, respectively. The method further includes steps for properly incrementing the device and group counters so that additional memory devices on the channel may be read and grouped.

Abstract: A driver to provide low voltage swings on a bus with fast switching times, the driver comprising two pairs of pullup and pulldown nMOSFETs, each pair operated in complementary fashion to each other, each pair with a high voltage rail at a smaller voltage than the data input logic HIGH voltage, and where each substrate of the nMOSFETs are biased so as to reduce their threshold voltages.