Abstract: A memory circuit, such as a cache or register file, where the keeper functional units are digitally controlled to compensate for variable sub-threshold leakage current.

Abstract: A high bandwidth, single stage, low power cascode transimpedance amplifier for short haul optical links. In one embodiment, an input signal is fed into the source of a common-gate pMOSFET, the output signal is taken at the drain of the common-gate pMOSFET, and bias current is supplied by a pMOSFET and a nMOSFET biased in their triode regions.

Abstract: An Ethernet switch using a hash table for address lookup. The hash function is based upon taking a slice of the coefficients of a remainder polynomial obtained after dividing the sum of an address polynomial and a shifted key polynomial by a cyclic redundancy check (CRC) polynomial. The hash table has multiple buckets for each hash table address. The switch may adaptively choose different CRC polynomials for polynomial division or different slices of the remainder polynomials to reduce bucket leakage.

Abstract: Various bus trace topologies are provided which allow for shorter stub lengths, reduced motherboard costs, more efficient routing between multiple agents, and bus traces with better matched characteristic impedances.

Abstract: An integrated circuit package and land side capacitor with reduced power delivery loop inductance. The capacitor pads have vias that lie underneath the land side capacitor, and have interposed digits.

Abstract: Electrostatic discharge protection is provided to an integrated circuit in which, for a particular embodiment, the integrated circuit comprises a switched capacitor circuit having a plurality of groups of voltage reference input ports; and a plurality of electrostatic discharge resistors coupled to a pad, wherein each electrostatic discharge resistor is coupled to a unique group of voltage reference input ports.

Abstract: For a memory cell, where an access transistor couples the memory cell to a local bit line, a pMOSFET essentially eliminates sub-threshold leakage current in the access transistor when the memory cell is not being read, and when the memory cell is being read, an additional pMOSFET essentially eliminates sub-threshold leakage current in the access transistor if the memory cell stores an information bit such that it does not discharge the local bit line. In this way, a half-keeper connected to the local bit line does not need to contend with sub-threshold leakage current.

Abstract: A high bandwidth, single stage, low power cascode transimpedance amplifier for short haul optical links. In one embodiment, an input signal is fed into the source of a common-gate pMOSFET, the output signal is taken at the drain of the common-gate pMOSFET, and bias current is supplied by a pMOSFET and a nMOSFET biased in their triode regions.

Abstract: A memory system comprising an expansion buffer and a memory expansion channel for connecting a large array of memory devices, such as Direct RDRAMs, to a memory controller. The memory devices are partitioned into subsets of memory devices so that each subset is connected to a unique memory channel for sending and receiving data. The expansion buffer and memory expansion channel provide communication with the memory devices via control packets on the expansion bus, where each control packet has a channel identification field to store a channel identifier; and via request packets on the expansion bus, where each request packet is associated with a control packet. The expansion buffer routes a request packet to a unique channel based upon the channel identifier stored in the associated control packet.

Abstract: A speed-locked loop (SLL) circuit to automatically determine overall chip speed, which is a function of the combination of supply voltage, temperature, and processing parameters, and to output the speed information in digital form to speed-compensating circuits in order to significantly reduce their sensitivity to operating conditions. Through negative feedback, a digitally controlled ring oscillator (DCO) is forced to lock at an oscillation frequency close to that specified by a six-bit speed constant input. A three-bit control bus varies the DCO oscillation frequency under digital control until the SLL achieves lock. When the SLL has achieved lock it latches the DCO control bus and outputs it as the speed information. The speed constant input may be varied under software control in order to determine the speed constant value that optimizes performance of speed-compensating circuits under SLL control.

Abstract: A method and apparatus for limiting a processor clock frequency includes an overclocking prevention circuit. The overclocking prevention circuit includes a frequency limiting circuit having programmable fusible elements. The frequency limiting circuit outputs a signal identifying a maximum processor clock frequency based on the state of each of the fusible elements. A comparator circuit compares a selected processor clock frequency to the maximum processor clock frequency to determine if the selected processor clock frequency is permitted. If the selected processor clock frequency is not permitted, then the processor is not allowed to operate at the selected clock frequency.

Abstract: A multiple input, fully differential amplifier. Embodiments make use of complementary differential transistors pairs connected with cascode transistors to form folded cascode pairs, to achieve wide common mode range, high common mode rejection, and high gain.

Abstract: A color filter array for CMOS and CCD image sensor applications, the color filter array having a tiling pattern of cyan, magenta, yellow, and blue pass filters. An imaging device with this color filter array provides signals in a CMYB color space.

Abstract: An embodiment of a full-swing, source-follower leakage tolerant dynamic logic gate comprises an nMOSFET logic to conditionally charge a node during an evaluation phase, and to charge the node to a relatively small voltage during the pre-charge phase so that the nMOSFET logic becomes reverse-biased.

Abstract: A computer architecture for collapsing dependency graphs for colliding store and load instructions. Many-to-one mappings are provided between logical registers and physical registers, so that more than one logical register may map to the same physical register. For a load instruction that is predicted to collide with an earlier in-flight store instruction, the destination logical register of the load instruction is mapped to the same physical register to which the source logical register of the earlier in-flight store instruction is mapped. A many-to-one mapping may be realized by associating a counter with each physical register, so that the value of a counter indicates whether its associated physical counter is free.

Abstract: Various bus trace topologies are provided which allow for shorter stub lengths, reduced motherboard costs, more efficient routing between multiple agents, and bus traces with better matched characteristic impedances.

Abstract: A discrete-time analog filter, where a filter tap of the filter comprises a voltage-to-current converter and a current multiplier in a single stage so as to provide a current signal indicative of a weighted sampled voltage signal. The current signals are summed by one or more active cascode differential latches to provide an output logic signal indicative of the filtered output. The discrete-time analog filter finds applications in channel equalization, and is suitable for high data rates and low voltage applications. The voltage and current signals may be differential.

Abstract: A cache memory cell comprising a read-access transistor to access the cell, where the read-access transistor is reverse biased when the memory cell is not being read to reduce sub-threshold leakage current.

Abstract: Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

Abstract: A multi-MAC chip for an Ethernet, the multi-MAC chip generating different random variables for each MAC layer so that each MAC has a distinct backoff interval when there is a collision. This avoids a possible live-lock state. In one embodiment, the random variables are generated by adding distinct numbers to a random variable generated according to the truncated binary exponential backoff algorithm. In another embodiment, each MAC stops a free-running counter for some specified number of clock cycles upon occurrence of a distinct event, and each counter for each colliding MAC is sampled upon a collision to provide random integers used to calculate backoff intervals for each colliding MAC.