Abstract: An apparatus for providing link layer security in a Physical Layer Transceiver (PHY) is disclosed. In one embodiment, the apparatus may comprise analog circuitry configured to interface with a data transmission medium, digital circuitry configured to interface with a Media Access Controller (MAC); and an crypto engine coupled to the digital circuitry.

Abstract: An improved substrate support system for clamping spring loaded pins that support substrates, such as printed circuit boards, which have even profiles, and uneven profiles due to components being installed on one side during manufacturing operations to the opposite side of the substrate. The substrate support system can utilize a cam lever, a knob, or a draw latch to move a clamping plate between an aligned position and a clamping position.

Abstract: A method for generating a substantially sinusoidal waveform containing encoded digital data having one of a first value and a second value at selected phase angles ?n comprises generating the waveform having an amplitude Y defined by a first function at phase angles lying outside of data regions, the first function being Y=sin ?; generating the waveform having an amplitude Y defined by the first function at phase angles lying inside the data regions having a range of ?? beginning at each phase angle ?n where data of the first value is to be encoded; and generating the waveform having an amplitude Y defined by a second function different from Y=sin ? at phase angles lying inside the data regions having a range of ?? associated with each phase angle ?n where data of the second value is to be encoded. The third harmonic of the waveform may be generated and used.

Abstract: A method for generating a substantially sinusoidal waveform containing encoded digital data having one of a first value and a second value at selected phase angles ?n comprises generating the waveform having an amplitude Y defined by a first function at phase angles lying outside of regions having a range ?? beginning at each phase angle ?n, said first function being Y=sin ?; generating the waveform having an amplitude Y defined by the first function at phase angles lying inside the regions having a range of ?? beginning at each phase angle ?n where data of the first value is to be encoded; and generating the waveform having an amplitude Y defined by a second function at phase angles lying inside the regions having a range of ?? associated with each phase angle ?n where data of the second value is to be encoded, the second function being different from Y=sin ?.

Abstract: An apparatus for generating a function activation signal to activate a function in an integrated circuit device comprises a power-on circuit receiving a power input and initializing and generating a test activation signal, a test circuit receiving the test activation signal and generating a test result signal, and a threshold decision circuit receiving the test result signal and generating the function activation signal. The test circuit models a function of the integrated circuit device and generates the test result signal when the power input has reached a sufficient voltage to perform the function of the integrated circuit device. The threshold decision circuit generates the function activation signal if the test result signal indicates the power input has reached a sufficient voltage to perform the function of the integrated circuit device.

Abstract: A method for generating a substantially sinusoidal waveform containing encoded digital data having one of a first value and a second value at selected phase angles ?n comprises generating the waveform having an amplitude Y defined by a first function at phase angles lying outside of regions having a range ?? beginning at each phase angle ?n, said first function being Y=sin ?; generating the waveform having an amplitude Y defined by the first function at phase angles lying inside the regions having a range of ?? beginning at each phase angle ?n where data of the first value is to be encoded; and generating the waveform having an amplitude Y defined by a second function at phase angles lying inside the regions having a range of ?? associated with each phase angle ?n where data of the second value is to be encoded, the second function being different from Y=sin ?.

Abstract: A high-voltage charge pump circuit includes a charge pump circuit. A first high-voltage output circuit is configured to set an output voltage of the charge pump at a first voltage level selected for regular programming and erasing memory cells. A second high-voltage output circuit is configured to set the output voltage of the charge pump at a second voltage level selected for walkout of device junctions, the second voltage level being higher than the first voltage level. A third high-voltage output circuit is configured to set the output voltage of the charge pump at a third voltage level selected for guardband programming and erasing, the third voltage level being lower than the second voltage level and higher than the first voltage level. Selection circuitry selectively couples one of the first, second, and third high-voltage output circuits to the output of the high-voltage charge pump circuit.

Abstract: A method for sensing voltage on an internal node in an integrated circuit includes applying a voltage larger than a threshold value to a first pad, generating from the activation voltage a potential for a sensing circuit and coupled to the internal node, and coupling an output of the sensing circuit to a second pad on the integrated circuit when the activation voltage is present on the first pad. A sensing circuit includes first and second pads, a voltage-sensor circuit having an input coupled to an internal node and a power connection coupled to a sensor power node. A circuit is configured to place a supply potential on the sensor power node when a threshold value is on the first pad. A switch coupled between the sensing circuit and the second pad turns on when the supply potential is on the voltage sensor power node.

Abstract: A printed circuit board assembly utilizing an elevated track to support signal lines between components is disclosed. The track rests on a plurality of vertical supports, placed amid the components, such that the signal lines can be routed after the components are configured on the board. The vertical supports can be installed at grounding holes already present on the printed circuit board assembly. The track is sufficiently rigid to support bundles of signal lines over long spans between vertical supports. The track can be constructed of the same material as the board, to provide the same ESD and conductivity characteristics as the board, as well as ensure that the track does not contribute to the EMI signature of the board.

Abstract: A method for storing data on nodes in memory cells of a non-volatile memory cell array including steps of setting non-volatile devices of the non-volatile memory cell array to a desired state, biasing pull-up devices and non-volatile devices in a first set of rows of the non-volatile memory cell array to an off state, loading data onto column lines of the non-volatile memory cell array and biasing non-volatile devices in a second set of rows in the memory cells of the non-volatile memory cell array to store data from the column lines on the nodes in the memory cells of the non-volatile memory cell array.

Abstract: A method for generating a substantially sinusoidal waveform containing encoded digital data having one of a first value and a second value at selected phase angles ?n comprises generating the waveform having an amplitude Y defined by a first function at phase angles lying outside of regions having a range ?? beginning at each phase angle ?n, said first function being Y=sin ?; generating the waveform having an amplitude Y defined by the first function at phase angles lying inside the regions having a range of ?? beginning at each phase angle ?n where data of the first value is to be encoded; and generating the waveform having an amplitude Y defined by a second function at phase angles lying inside the regions having a range of ?? associated with each phase angle ?n where data of the second value is to be encoded, the second function being different from Y=sin ?.

Abstract: A method for generating a substantially sinusoidal waveform containing encoded digital data having one of a first value and a second value at selected phase angles ?n comprises generating the waveform having an amplitude Y defined by a first function at phase angles lying outside of regions having a range ?? beginning at each phase angle ?n, said first function being Y=sin ?; generating the waveform having an amplitude Y defined by the first function at phase angles lying inside the regions having a range of ?? beginning at each phase angle ?n where data of the first value is to be encoded; and generating the waveform having an amplitude Y defined by a second function at phase angles lying inside the regions having a range of ?? associated with each phase angle ?n where data of the second value is to be encoded, the second function being different from Y=sin ?.

Abstract: A surgical sponge identification system for a set of surgical sponges comprising each sponge in the set having an exterior surface, each sponge bearing on the exterior surface a unique indicium from a set of indicia uniquely identifying the set.

Abstract: A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A real-time clock is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A programmable logic block is coupled to the clock conditioning circuit and the real-time clock.

Abstract: The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU).

Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

Abstract: A zero maintenance pump includes a motor having a motor housing and a motor drive shaft rotatably mounted in the motor housing. A shaft extension is coupled to the motor drive shaft distal from the motor housing. A coupling element has a body with a first end and a second end opposite the first end. The body includes a body wall defining an interior and an exterior. At least one slot is formed in the body wall. The coupling element includes a flange coupled to the body wall proximate the first end. The coupling element is coupled to the motor housing at the flange proximate the motor drive shaft and the coupling element is disposed over the shaft extension. A mesh element is coupled to the body wall at the exterior. A pump is coupled to the coupling element proximate the second end.

Abstract: A charge pump generates a voltage higher than an intermediate voltage and a regulator circuit provides a first regulated voltage higher than the intermediate voltage. A second stage includes a regulator stage using the first voltage to provide the intermediate voltage from the first voltage. A charge pump provides a pump output voltage. The pump output voltage is divided and the divided voltage is presented to a first comparator that compares it with a reference voltage. The first comparator drives the gate of a first MOS transistor to regulate the pump output voltage to a regulated voltage related to the reference voltage. The regulated voltage is presented to a second comparator that compares it with the reference voltage. The second comparator drives the gate of a second MOS transistor to downconvert the regulated output voltage to an intermediate voltage related to the reference voltage.

Abstract: A programmable analog circuit includes a plurality of analog inputs, a differential analog buffer, a digital-to-analog converter, an analog-to-digital converter, and an operational amplifier having an inverting input and a non-inverting input. An analog switching network is coupled between the plurality of analog inputs, the differential analog buffer, the digital-to-analog converter, the analog-to-digital converter, and the operational amplifier and is configured to allow programmable connections from any of the plurality of analog inputs, the differential analog buffer, and the digital-to-analog converter to the inverting input and a non-inverting input; of the operational amplifier. An array of programmable logic is programmably coupled to the input to the digital-to-analog converter and the output of the analog-to-digital converter.

Abstract: A turning structure for routing channels in a field programmable gate array, comprising a first plurality of routing channels having a first direction and a second plurality of routing channels having a second direction. The first plurality of routing channels intersects the second plurality of routing channels to form a plurality of matrices of intersecting interconnect conductors in the routing channels. A first number of reprogrammable elements is disposed at intersections in at least one of the plurality of matrices, a second number of reprogrammable elements disposed at intersections in at least one of the plurality of matrices. The second number of reprogrammable elements is greater than the first number of reprogrammable elements, and a third number of reprogrammable elements disposed at intersections in at least one of the plurality of matrices. The third number of reprogrammable elements is greater than the second number of reprogrammable elements.