Abstract: A method and apparatus for presenting a plurality of link devices as separate nodes within a single serial bus module by generating individual or a distinct configuration ROM image for each link device in the module. Each configuration ROM includes an entry for a distinct identifier representing the corresponding link device thereby creating a one to one mapping of link device to node via the distinct configuration ROM.

Abstract: A method and apparatus for adding and updating protocol inspection knowledge/information to a firewall system during operation and without interrupting firewall services. The invention allows inspection modules, which contain protocol information, to be added and updated to the system without requiring a service restart of the firewall system.

Abstract: A method for providing a circuit for selectively interconnecting N pairs of nodes in an integrated circuit device comprising: providing a memory array having a plurality of wordlines and a plurality of bitlines; providing a plurality of dynamic random access memory wordlines; providing a separate switch for each pair of nodes in the integrated circuit, each switch associated with a unique combination of one of the plurality of bitlines and one of the plurality of dynamic random access memory wordlines, each switch including a refresh transistor and a switching transistor; and providing an address decoder having at least N distinct states for supplying signals to the plurality of wordlines and the plurality of dynamic random access memory wordlines.

Abstract: The present disclosure relates to a ride for providing an upward boost to a participant jumping up and down. The flexible rods of this disclosure may be articulated by a base thereby imparting tension in the flexible rods, and providing an upward force to a participant jumping up and down. Additionally, elastic pods may be provided, allowing participants to bounce upward in a addition to the lift provided by the flexible members, thereby enhancing the participant's experience.

Abstract: The disclosed device is directed towards a shadow mask for ion beams comprising a silicon wafer with a hole pattern arranged therein, wherein the silicon wafer is provided at a side confronting the incident ion beams with a metallic coating which stops the ion beams and dissipates heat, wherein an apertured region of the silicon wafer has a thickness from about 20 ?m to about 200 ?m and apertures in the shadow mask have lateral dimensions from about 0.5 ?m to about 3 ?m.

Abstract: The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU).

Abstract: A non-reciprocal nephelometer is disclosed herein that uses an integrating sphere with attached truncation-reduction tubes to contain the sample volume and to integrate the scattered light. The disclosed nephelometer improves on the imperfect angular response by using an integrating sphere design with forward (backward) truncation angles of ?1° (?179°), it reduces sampling losses by employing a substantially straight vertical flow path. In one disclosed embodiment, an illumination assembly consisting of one or multiple diffuse light sources is provided for homogenously illuminating the integrating sphere. An illumination aperture admits light from the light sources, a sensing aperture admits scattered light to an optical detector, and a dark aperture provides a dark background viewing area for the optical detector.

Abstract: A circuit for limiting a power current from a power-controlling pass device, the power-controlling pass device being coupled to a supply voltage, comprises the following. A sense device is coupled to the supply voltage with the sense device being configured to draw a sense current that is proportional to the power current. A current mirror is coupled to the sense device and the supply voltage through a low impedance node, the current mirror being configured to draw a mirror current through the low impedance node that is relative to the sense current. A limiting device is coupled to the supply voltage, the power-controlling pass device, and the low impedance node, the limiting device being configured to limit the power current according to a voltage difference between the low impedance node and the supply voltage. A resistance device or PMOS transistor that generates the voltage difference and that may be controlled through a proper bias circuit to adjust the voltage difference.

Abstract: A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.

Abstract: A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.

Abstract: A method and system for externally managing router configuration data in conjunction with a centralized database subsystem in a router device. The centralized database provides external management registration and unregistration for various managing router subsystems associated with said database system. The centralized database and the subsystems registered for external data management engage in transaction request sequences to provide router data requested by other client subsystems. The arrangement of the various client subsystems associated with the database subsystem allows the client subsystems to remain modular and independent of each other.

Abstract: A method for erasing a non-volatile memory cell interconnect switch in an FPGA comprises providing an FPGA having a core containing a plurality of non-volatile-memory-cell interconnect switches, each switch formed in a switch well region and coupled to a source/drain of an n-channel transistor formed in a grounded well region separate from the switch well region. A non-volatile memory cell interconnect switch is selected for erasing. The switch well region is disconnected from ground. A VCC potential is applied to the switch well region and to the drain of the n-channel transistor to which it is coupled and an erase potential is applied to the gate of the selected non-volatile memory cell interconnect switch.

Abstract: The invention is a system for selecting a peripheral, the peripheral receiving a first clock frequency. The invention comprises the following. A processing circuit receives a second clock frequency, where the first and second clock frequencies are different. The processing circuit is configured to transmit a select signal. A bridge circuit is coupled to the processing circuit and the peripheral, and is configured to receive the select signal and transmit a peripheral select signal to the peripheral. The bridge circuit is further configured to receive the second clock frequency but not the first clock frequency. A counter is coupled to the bridge circuit and is configured to process a count, the count being a predetermined number and based on the value of the first frequency.

Abstract: An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.

Abstract: A phase-preserving amplification system for stellar interferometers is disclosed. In one embodiment, a pair of crystals are provided that are configured to receive an optical signal from a source such as a telescope. A pump inputs a high energy field into the crystals, amplifying the optical signals using optical parametric amplification (OPA). A beam combiner receives and combines the amplified signals and a data collection element collects the combined amplified signals.

Abstract: A carrier for a semiconductor die has a substrate with a cavity formed in the substrate. The cavity has a bottom and sidewalls, and the sidewalls have a stepped tier. Electrically conductive contacts are disposed on an underside of the substrate. Electrically conductive tabs are disposed on the stepped tier, and electrically conductive external bond terminals are disposed on an edge of the substrate. Electrically conductive paths are formed in the substrate and electrically coupled between the electrically conductive tabs, the electrically conductive contacts, and the electrically conductive external bond terminals.

Abstract: An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture.

Abstract: A first voltage divider includes a first resistor having a first resistance coupled to a positive voltage reference in series with a second resistor having a second resistance and coupled to ground. A second voltage divider includes a third resistor having the first resistance coupled to the positive voltage potential in series with a fourth resistor having the second resistance, and a fifth resistor having a third resistance and coupled to a negative voltage. A comparator has an inverting input coupled to the junction of the first and second resistors and a non-inverting input coupled to the junction of the third and fourth resistors. The first and third resistors are equal and the second and fourth resistors are equal. The fifth resistor has a value chosen to drop a voltage equal to the target voltage to be regulated when the voltage regulator output is equal to that target voltage.

Abstract: The disclosed device is directed toward an anti-terrorist aircraft pilot sensor system. The anti-terrorist aircraft pilot sensor system comprises a pilot sensor including at least one of a biometric sensor and a physiological sensor. An input component is operatively coupled to the pilot sensor. An aircraft central processor unit is operatively coupled to the pilot sensor. The aircraft central processor unit includes a transceiver operatively coupled to the aircraft central processor unit. The anti-terrorist aircraft pilot sensor system comprises an autopilot of the aircraft operatively coupled to the aircraft central processor unit. A ground control located remote from the aircraft is operatively coupled to the aircraft central processor unit. The ground control includes a transceiver coupled to the ground control. An aircraft override is operatively coupled to the ground control and operatively coupled to the aircraft central processor unit.

Abstract: An integrated multi-function analog circuit includes at least one MOSFET gate-drive circuit coupled to a first I/O pad. At least one voltage-sensing circuit is coupled to a second I/O pad. At least one current-sensing circuit is coupled to the second I/O pad and a third I/O pad. At least one temperature-sensing circuit is coupled to a fourth I/O pad.