Patents Represented by Attorney Sierra Patent Group, Ltd.
  • Patent number: 7271502
    Abstract: The disclosed device is directed towards a combined network switch and power strip including a housing defining an interior and an exterior. A power cord is coupled to the housing. A power surge protector coupled to the power cord is disposed in the housing. An electrical power switch is coupled to the surge protector and is disposed in the housing. An array of electrical outlets is coupled to the electrical power switch and is disposed in the housing in operative communication between the interior and the exterior. A power transformer is coupled to the power surge protector in the housing interior. A network switch is coupled to the power transformer and is disposed in the housing interior. The network switch includes a network port array in operative communication between the interior and the exterior. A network connection is in operative communication with the network switch and a network outlet.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: September 18, 2007
    Assignee: Cisco Technology, Inc.
    Inventor: Phillip Andrew Remaker
  • Patent number: 7269814
    Abstract: The present invention comprises apparatus and a method for simultaneously programming multiple antifuses in a multiple tile field programmable gate array (FPGA). The invention comprises an FPGA having a plurality of logic modules with programmable elements. The logic modules are partitioned into a plurality of individually programmable groups and an isolation device may be coupled between the individually programmable groups of logic modules such that each of the programmable elements in each of the plurality of individually programmable logic modules may be programmed concurrently.
    Type: Grant
    Filed: September 18, 2006
    Date of Patent: September 11, 2007
    Assignee: Actel Corporation
    Inventors: Shin-Nan Sun, Wayne W. Wong
  • Patent number: 7268589
    Abstract: An address transition detector circuit includes an input node, an output node, a bandgap reference node, and Pbias and Nbias nodes having voltages derived from the bandgap reference node. First through fifth cascaded inverters are each powered by a p-channel and n-channel MOS bias transistors having their gates coupled respectively to the Pbias node and the Nbias node. The input of the first inverter is coupled to the input node. First and second capacitors are coupled respectively to ground from the outputs of the first and fourth cascaded inverters. A NAND gate has a first input coupled to the input node, a second input coupled the output of the fifth cascaded inverter, and an output coupled to the output node.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: September 11, 2007
    Assignee: Actel Corporation
    Inventors: Poongyeub Lee, Ming-Chi Liu
  • Patent number: 7269704
    Abstract: The invention comprises a system for reducing inactive periods in an integrated circuit. The integrated circuit is coupled to an external peripheral by an external data bus. The integrated circuit has a processor coupled to an internal data bus. The system comprises the following. An external bus circuit is coupled to the internal and external data busses. The bus interface circuit is configured to receive read and write signals for data request data. In response, the bus interfaces circuit transmits a wait signal until data from the external peripheral is available on the internal data bus. The wait signal indicates that the external and internal data busses are not available for other purposes. After the processor has received or transmits the data, the bus interface circuit stops transmitting the wait signal and transmits a busy signal. The busy signal indicates that the internal data bus is available and the external data bus is not available for other purposes.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: September 11, 2007
    Assignee: Atmel Corporation
    Inventors: Eric Matulik, Nicolas Rescanieres, Anne Lafage
  • Patent number: 7269591
    Abstract: A web server for providing a pay-for-service web site is disclosed configured to execute an HTML front-end entry process configured for creating and storing a personal homepage for a owner. The web server is also configured to receive a fee for making the personal homepage accessible on a network.
    Type: Grant
    Filed: May 11, 2004
    Date of Patent: September 11, 2007
    Assignee: GraphOn NES Sub, LLC.
    Inventors: Ralph E. Wesinger, Jr., Christopher D. Coley
  • Patent number: 7268585
    Abstract: An aggregation interconnect scheme for a programmable logic device provides low-skew routing of high fan-out signals by aggregating regional routing resources, which provide low-skew routing utilizing under-utilized global routing resources.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: September 11, 2007
    Assignee: Actel Corporation
    Inventor: Alan B. Reynolds
  • Patent number: 7269847
    Abstract: A remote configurator for a gateway device is disclosed. The remote configurator module is operatively disposed in a gateway device for providing network connectivity between a source and destination of IP-compliant traffic. Embodiments of the remote configurator module are disclosed providing an HTML-based configuration interface for allowing remote management of gateway configuration files over an IP-compliant connection.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: September 11, 2007
    Inventors: Ralph E. Wesinger, Jr., Christopher D. Coley
  • Patent number: 7266742
    Abstract: An apparatus for providing a local scan enable signal. The local scan enable signal being used to perform an at-speed test on a portion of circuitry associated with the local scan enable signal. The local scan enable signal is generated from a global scan enable signal and clock signal. The global scan enable signal and clock signal are received from the system and used to generate a local scan enable signal to test each portion of circuitry in the die at speed.
    Type: Grant
    Filed: April 6, 2004
    Date of Patent: September 4, 2007
    Assignee: Cisco Technology, Inc.
    Inventor: Kamleshkumar Sureshchandra Pandey
  • Patent number: 7260378
    Abstract: A locator system for processing commercial 911 requests is disclosed. An e911-enabled wireless network including a switching center is configured to route emergency 911 calls to a Public Safety Answering Point (PSAP); and is further configured to receive a commercial 911 request from the mobile station, and then route the commercial request to a location other than the PSAP. The routing of the commercial 911 request may be accomplished using a protocol indicating that the 911 request is of a commercial nature.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: August 21, 2007
    Inventors: Bryan Holland, Timothy A. Brisson
  • Patent number: 7256610
    Abstract: A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and temperature sensing and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with temperature measuring and control circuitry performs temperature measurement and control functions and can be used to create an on-chip temperature log.
    Type: Grant
    Filed: May 19, 2004
    Date of Patent: August 14, 2007
    Assignee: Actel Corporation
    Inventors: Rabindranath Balasubramanian, Limin Zhu, Gregory Bakker
  • Patent number: 7252230
    Abstract: Systems and method for dynamically tracking assets located in different geographic zones are disclosed. Disclosed embodiments include a central zone hosting an inventory system. The inventory system is in network communication with remote zones that include sensors for interrogating tagged assets located in the zones. The inventory system is configured to poll the remote zones to obtain information regarding the tagged assets and store the information in a database. The inventory system may then determine whether any of the received information deviates from an expected result, and take appropriate action in response to the deviation.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: August 7, 2007
    Assignee: Cisco Technology, Inc.
    Inventors: Waseem Aman Sheikh, Brian P. Suckow, Dave Evans
  • Patent number: 7248032
    Abstract: A low capacitance measurement probe having an outer conductor forming an outer wall; a non-conductive spacer forming a first wall between a conductive layer and the outer conductor; the conductive layer forming a second wall coupled to the interior of the first wall; an insulating layer forming a third wall coupled to the interior of the second wall; and an inner conductor forming an inner wall coupled to the interior of the third wall. The probe may include a knob or a button in the inner conductor at a tip of the probe to increase the surface area of the inner conductor in order to the sensitivity of the probe.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: July 24, 2007
    Assignee: BioLuminate, Inc.
    Inventors: Richard Hular, Liuz B. Da Silva, Charles L. Chase, Bruce W. Haughey
  • Patent number: 7249376
    Abstract: The present invention provides a firewall that achieves maximum network security and maximum user convenience. The firewall employs “envoys” that exhibit the security robustness of prior-art proxies and the transparency and ease-of-use of prior-art packet filters, combining the best of both worlds. No traffic can pass through the firewall unless the firewall has established an envoy for that traffic. Both connection-oriented (e.g., TCP) and connectionless (e.g., UDP-based) services may be handled using envoys. Establishment of an envoy may be subjected to a myriad of tests to “qualify” the user, the requested communication, or both. Therefore, a high level of security may be achieved. The usual added burden of prior-art proxy systems is avoided in such a way as to achieve fall transparency-the user can use standard applications and need not even know of the existence of the firewall. To achieve full transparency, the firewall is configured as two or more sets of virtual hosts.
    Type: Grant
    Filed: November 7, 2003
    Date of Patent: July 24, 2007
    Assignee: GraphOn Nes Sub, LLC
    Inventors: Ralph E. Wesinger, Jr., Christopher D. Coley
  • Patent number: 7249378
    Abstract: The present invention provides a firewall that achieves maximum network security and maximum user convenience. The firewall employs “envoys” that exhibit the security robustness of prior-art proxies and the transparency and ease-of-use of prior-art packet filters, combining the best of both worlds. No traffic can pass through the firewall unless the firewall has established an envoy for that traffic. Both connection-oriented (e.g., TCP) and connectionless (e.g., UDP-based) services may be handled using envoys. Establishment of an envoy may be subjected to a myriad of tests to “qualify” the user, the requested communication, or both. Therefore, a high level of security may be achieved. The usual added burden of prior-art proxy systems is avoided in such a way as to achieve fall transparency—the user can use standard applications and need not even know of the existence of the firewall. To achieve full transparency, the firewall is configured as two or more sets of virtual hosts.
    Type: Grant
    Filed: November 3, 2003
    Date of Patent: July 24, 2007
    Assignee: GraphOn Nes Sub, LLC
    Inventors: Ralph E. Wesigner, Christopher D. Coley
  • Patent number: 7245535
    Abstract: A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: July 17, 2007
    Assignee: Actel Corporation
    Inventors: John McCollum, Hung-Sheng Chen, Frank Hawley
  • Patent number: 7244633
    Abstract: A carrier for a semiconductor die has a substrate with a cavity formed in the substrate. The cavity has a bottom and sidewalls, and the sidewalls have a stepped tier. Electrically conductive contacts are disposed on an underside of the substrate. Electrically conductive tabs are disposed on the stepped tier, and electrically conductive external bond terminals are disposed on an edge of the substrate. Electrically conductive paths are formed in the substrate and electrically coupled between the electrically conductive tabs, the electrically conductive contacts, and the electrically conductive external bond terminals.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: July 17, 2007
    Assignee: Actel Corporation
    Inventor: Raymond Kuang
  • Patent number: 7243950
    Abstract: The present invention relates to an adjustable seat belt guide (15) which is constructed of a clamping belt (5) around the back support (6) of a car seat (4) in a vertical way and supplied with a tightening retaining clip (7) for a taut fastening, in which through a cover (8) around the clamping belt (5) a rectangular carabiner or other inventable locking mechanism (10) provided with a lockable opening, preferably a turnable bush (11) is attached, in which the car seat belt (1) is applied through the locking mechanism (10) so that a very comfortable complete car seat belt assembly is created for a pleasant ride.
    Type: Grant
    Filed: August 13, 2002
    Date of Patent: July 17, 2007
    Assignee: Solid Jacqed I BV
    Inventor: Veronique Therese Josephine Marguerite Kooter Lenders
  • Patent number: 7242226
    Abstract: A system and method for reducing forward inadvertent biasing of a switch having a transistor. The gate of the transistor is connected to ground and a voltage source less than ground. A control signal of the gate is then applied to a level translator to compensate for the voltage applied to the gate.
    Type: Grant
    Filed: August 3, 2004
    Date of Patent: July 10, 2007
    Assignee: Cisco Technology, Inc.
    Inventor: Theodore Hogeland Conard, III
  • Patent number: 7242242
    Abstract: A current mirror comprising: current source; a first p-channel transistor having a source coupled to operating potential, and a gate and drain coupled to current source; a second p-channel transistor having a source coupled to operating potential, a gate coupled to gate of first p-channel transistor, and a drain; a zero-threshold p-channel transistor having a source coupled to drain of second p-channel transistor, a gate coupled to gate of first p-channel transistor, and a drain; a first n-channel transistor having a source coupled to ground, and a gate and drain coupled to drain of zero-threshold p-channel transistor; a second n-channel transistor having a source coupled to ground, a gate coupled to gate of first n-channel transistor, and a drain; and a zero-threshold n-channel transistor having a source coupled to drain of second n-channel transistor, a gate coupled to gate of first n-channel transistor, and a drain coupled to current-output node.
    Type: Grant
    Filed: March 29, 2006
    Date of Patent: July 10, 2007
    Assignee: Atmel Corporation
    Inventors: Lorenzo Bedarida, Danut Manea, Mirella Marsella, Andrea Sacco
  • Patent number: 7240126
    Abstract: The present disclosure presents a system for parsing based upon content type, and provides a content-rich set of parsing rules that can be optimized for a wide variety of applications. The present system also recognizes different types of content in addition to text, such as behaviors, and associates rules to parse a wide variety of content. The parser may be downloaded to a number of clients by the server, and content may be parsed locally by the clients in a manner similar to the server.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: July 3, 2007
    Inventors: Andrew Cleasby, Ryan Schuft