Abstract: A current mirror comprising: a current source; a first p-channel MOS transistor having a source coupled to an operating potential, and a gate and a drain coupled to the current source; a second p-channel MOS transistor having a source coupled to the operating potential, a gate coupled to the gate of the first p-channel transistor, and a drain; a first n-channel MOS transistor having a source coupled to ground, and a gate and a drain coupled to the drain of the second p-channel transistor; a zero-threshold n-channel MOS transistor having a drain coupled to a current-output node, a gate coupled to the gate of the first n-channel transistor, and a source; and a second n-channel MOS transistor having a source coupled to ground, and a gate coupled to the gate of the first n-channel transistor and a drain coupled to the source of the zero-threshold n-channel transistor.

Abstract: A method for determining the anatomic condition of components of the body of a human or of an animal is disclosed comprising producing a sound signal in a selected component of the body by at least one of passive and active movements of at least one joint. The method includes recording a sound signal at a point adjacent to the selected component of the body and evaluating the sound signal. An auxiliary device selected from the group consisting of a splint, an orthosis and an exercise machine is used which ensures a repeatable movement determined by the design of the auxiliary device. The sound signal caused by the movement is recorded and evaluated by a spectral analysis of frequencies and amplitudes contained in the sound signal. A comparison is made with reference patterns of the spectral analyses for the diagnosis of the anatomic condition.

Abstract: An FPGA architecture has top, middle and low levels. The top level is an array of B16×16 tiles enclosed by I/O blocks. The routing resources in the middle level are expressway routing channels including interconnect conductors. At the lowest level, there are block connect routing channels, local mesh routing channels, and direct connect interconnect conductors to connect the logic elements to further routing resources. Each B1 block includes four clusters of devices. Each of the clusters includes first and second LUT3s, a LUT2, and a DFF. Each of the LUT3s have three inputs and one output. Each of the LUT2s have two inputs and one output. Each DFF has a data input and a data output. In each of the clusters the outputs of the LUT3s are multiplexed to the input of DFF, and symmetrized with the output of the DFF to form two outputs of each of the clusters.

Abstract: Method and apparatus for generating and receiving an extended Vendor Specific Attribute (VSA) is disclosed. In one aspect, a extended format VSA may be generated containing at least a Vendor-Type field having a predetermined value and a Extended Vendor-Type field. A Vendor Specific Attribute packet generated and received in accordance with the teachings of this disclosure may have a field sequence of <Type> <Length> <Vendor-ID> <Vendor-Type> <Length> <Vendor-Extended-Type> <Value>, and may field lengths of Type=8 bits; Length=8 bits; Vendor-ID=32 bits; Vendor-Type 8 bits; Length=8 bits; Vendor-Extended-Type=32 bits; and Value=1 or more bytes.

Abstract: A method and apparatus for significantly reducing the number and types of non-volatile memory used on a typical motherboard is disclosed. While there are typically three or more types of non-volatile memory used to support the CPU during system boot and initialization, the present invention uses only one. This allows for a significant savings in materials cost and design effort.

Abstract: An advancing pen comprising an outer barrel; an inner chamber having an open end and a closed end, the closed end comprising a driving mechanism; a plurality of cartridges, each cartridge of the plurality containing marking contents, a cartridge tip for applying the contents to a surface, a seal to retain the contents within the cartridge, and a removable, protective cover placed over the seal and the cartridge tip, wherein the driving mechanism propels cartridges of the plurality in a serial manner to a position that partially exposes a cartridge through the opening such that the protective cover can be removed and the contents can be applied to the desired surface.

Abstract: Methods and apparatus are disclosed for dynamically updating service profiles in a network system. A device, such as an edge device providing network services to subscribers, is configured to dynamically update profiles for services provided to subscribers with no downtime required. Devices may be configured in accordance with this disclosure to receive a request by a first subscriber to access a network service having an associated service profile. The device may then cache the current version of the service profile into memory. Upon receiving a request from a second subscriber to access the same network service, the device may then determine whether a newer version of the service profile exists. If a newer version exists, then the device may then associate the newer version of the service profile to the second subscriber's session. Older versions may be purged as they are no longer used.

Abstract: The present invention comprises a field programmable gate array that has a plurality of dedicated first-in/first-out memory logic components. The field programmable gate array includes a plurality of synchronous random access memory blocks that are coupled to a plurality of dedicated first-in/first-out memory logic components and a plurality of random access memory clusters that are programmably coupled to the plurality of dedicated first-in/first-out memory logic components and to the plurality of synchronous random access memory blocks.

Abstract: A metal interconnect structure formed over a substrate in an integrated circuit that traverses a scribe-line boundary between a first die and a second die includes at least one metal interconnect line that traverses the scribe-line boundary. A switch is coupled between the at least one metal interconnect line and the substrate, the switch having a control element coupled to a scribe-cut control line. The control line turns the switch on if the two dice are separated into individual dice and turns the switch off if the two dice are to remain physically connected so that the interconnect line may be used to make connections between circuits on the two dice.

Abstract: A circuit for limiting a power current from a power-controlling pass device, the power-controlling pass device being coupled to a supply voltage, comprises the following. A sense device is coupled to the supply voltage with the sense device being configured to draw a sense current that is proportional to the power current. A current mirror is coupled to the sense device and the supply voltage through a low impedance node, the current mirror being configured to draw a mirror current through the low impedance node that is relative to the sense current. A limiting device is coupled to the supply voltage, the power-controlling pass device, and the low impedance node, the limiting device being configured to limit the power current according to a voltage difference between the low impedance node and the supply voltage.

Abstract: First and second complimentary static random-access-memory cell bit lines are coupled to first and second bit nodes through first and second access transistors controlled by a word line. A first inverter has an input coupled to the first bit node and an output coupled to the second bit node. A second inverter has an input coupled to the second bit node and an output coupled to the first bit node through a first transistor switch. A transistor switch is coupled between the output of a non-volatile memory cell and the first bit node. A control circuit coupled to the gate of the transistor switch. Either the drive level of the non-volatile memory cell is selected to overpower the output of the second inverter or the second inverter is decoupled from the first bit node while the output of the non-volatile memory cell is coupled to the first bit node.

Abstract: A method for manufacturing a semiconductor structure comprising clusters and/or nanocrystals of silicon described which are present in distributed form in a matrix of silicon compound. The method comprises the steps of depositing a layer of thermally nonstable silicon compound having a layer thickness in the range between 0.5 nm and 20 nm especially between 1 nm and 10 nm and in particular between 1 nm and 7 nm on a support and thermal treatment at a temperature sufficient to carry out a phase separation to obtain clusters or nanocrystals of silicon in a matrix of thermally stable silicon compound. The claims also cover semiconductor structures having such distributed clusters or nanocrystals of silicon The method described enables the economic production of high density arrays of silicon clusters or nanocrystals with a narrow size distribution.

Abstract: The present invention provides a dynamic chair having a deterministic motion path that allows a variety to different paths to be selected depending of needs of user. By changing the ratio between drive wheels that control the pitch and roll of the seat, motion paths can be selected to help a person assume and/or avoid certain postures while seated. Embodiments of the present invention move the seat of the dynamic chair through a deterministic path to dictate how often and when the seat is in a level position with respect to pitch and roll.

Abstract: A multi-directional routing repeater has a plurality of buffers, each of the plurality of buffers has an input and an output. The output of each of the plurality of buffers is connected to a separate routing line for transmitting a signal in a separate direction of a first set of routing lines, and the input of each of the plurality of buffers is connected to one of a first set of programmable switches, one of a second set programmable switches, one of a third set of programmable switches, and one of a fourth set of programmable switches, and each one of the first set of programmable switches is connected to a separate one of the second set of programmable switches and a separate one of the second set of programmable switches, none of which are connected to an input of a same one of the plurality of buffers. Each one of the first set of programmable switches is connected to a separate routing line for transmitting a signal in a separate direction of a second set of routing lines.

Abstract: An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture.

Abstract: A method and apparatus for communication between a mobile computer terminal and a host computer in a system in which it is necessary for the mobile computer terminal to send a message to the host computer at a particular time. The specific time at which the mobile computer terminal must send a message to the host computer is first determined. Then, a timer or clock is programmed to wake up the mobile computer terminal at the specific time. A sleep mode may be entered, which may be interrupted at the specific time to send the message. This will normally allow a mobile computer terminal to maintain its lease on an IP address despite being out of range of a wireless network.

Abstract: A method and apparatus for a communications system apparatus with an Ethernet backplane and at least one system processing engine (“SPE”) and a system manager SPE (“SMSPE”), for requesting chassis data from the SMSPE by the SPE and SMSPE. The method comprising: determining the IP address of the SMSPE; and issuing a request for Chassis Data to the SMSPE. Also, a method and apparatus for the communications system for sending chassis data from the SMSPE to the at least one SPE and SMSPE and verifying that the requesting SPE and SMSPE are part of the communications system.

Abstract: An apparatus for hearing protection comprising: a body having coupling means, said coupling means configured to attach to a body part; a sound sensor disposed in said body, said sound sensor configured to sense ambient sound; a sound processor coupled to said sound sensor, said sound processor configured to receive a sound signal from said sound sensor and generate a sound indicator signal; an indicator coupled to said sound processor and disposed in said body, said indicator configured to indicate sound levels, said indicator including at least one of a visual display and a tactile indicator, wherein said visual display visually indicates levels of sound and said tactile indicator indicates levels of sound through tactile means.

Abstract: A method of forming a field programmable gate array architecture having a plurality of input/output pads comprising: providing a plurality of logic clusters; providing a plurality of input/output clusters; providing a plurality of input/output buffers; providing a plurality of dedicated input/output first-in/first-out memory blocks, the dedicated input/output first-in/first-out memory blocks having a first-in/first-out memory coupled to one of the plurality of input/output pads; providing an input/output block controller programmably coupled to the plurality of dedicated input/output first-in/first-out memory blocks, wherein the input/output block controller comprises a dedicated FIFO flag logic block and an input/output FIFO block controller cluster; and providing a routing interconnect architecture programmably coupling the logic clusters, the input/output buffers and the input/output clusters, wherein the dedicated input/output first-in/first-out memory blocks are programmably coupled between the input/out

Abstract: In an integrated circuit, a radiation tolerant static random access memory device comprising a first inverter having an input and an output, a second inverter having an input and an output. A first resistor is coupled between the output of the first inverter and the input of the second inverter. A second resistor is coupled between the output of the second inverter and the input of the first inverter. A first write transistor is coupled to the output of the first inverter and has a gate coupled to a source of a first set of write-control signals and a second write transistor is coupled to the output of the second inverter and has a gate coupled to said source of a second set of write-control signals. Finally, a pass transistor has a gate coupled to the output of on of the first and second inverters.