Abstract: A protection circuit for use with a 1394-compliant network of devices is disclosed. The protection circuit comprises a power source, a switch connecting the protection circuit to power supplied by another device, a transceiver having at least one outbound data line, the at least one data line connected to an electrostatic discharge line, and a diode connected between the at least one outbound data line and the electrostatic discharge line.

Abstract: A safety lock system for a firearm comprising: a firearm having a hammer configured for firing said fire arm; a safety lock housing having a first end and a second end opposite said first end and an electronics package coupled to said housing, said first end configured to form a safety grip, said second end having a hammer end and a channel end; a safety rod coupled to said hammer end and configured for blocking said hammer; a first switch, having a first position and a second position, coupled to said channel end of said safety lock housing, and configured in said first position; and said electronics package, being configured for regulating said safety rod through said first switch.

Abstract: The apparatus comprises a repeatable non-uniform segmented routing architecture in a field programmable gate array having a plurality of sets of routing tracks having a first and last track position proceeding in a first direction and having at least one programmable element and at least one direct address device. The tracks are partitioned into uniform lengths and a track in the last position crosses over to a track in the first position immediately prior to said partition. The apparatus of the present system also has a plurality of sets of routing tracks having a first and last track position proceeding in a second direction. The tracks proceeding in the second direction have at least one programmable element and direct address device, wherein the tracks are partitioned into uniform lengths and said last track position crosses over to a first track position immediately prior to said partition.

Abstract: The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU).

Abstract: A tire cable chain system is disclosed. The tire cable chain system includes a continuous and unbroken outboard annular holder; a tensioning cable adapted to form at least one tensioning cross member and a continuous and unbroken inboard annular holder disposed in physical contact with the outboard annular holder; a first receiver guide disposed on the outboard annular holder and adapted to receive the tensioning cable; a second receiver guide disposed on the inboard annular holder and adapted to receive the tensioning cable; a hub having a tensioned spool shaft connected to the tension cable; at least one stabilizing cable connected to the hub and the outboard annular holder; and at least one cross member disposed at a physical connection between the outboard annular holder and the inboard annular holder.

Abstract: A gas pressurization system comprising a gas inlet valve configured to receive an inlet gas stream. A clean-up system is coupled to the gas inlet valve. A recovery heat exchanger coupled to the clean-up system. The recovery heat exchanger is configured to remove thermal energy from the inlet gas stream and cool the inlet gas stream to one of a pre-cooled gas and liquid stream. An expander coupled to the recovery heat exchanger is configured to expand the pre-cooled liquid stream. A refrigeration unit coupled to the expander and configured to cool the expanded pre-cooled liquid stream to a liquid phase. A buffer storage unit is coupled to the refrigeration unit. A pump is coupled to the buffer storage unit at a pump suction and has a pump discharge coupled to the recovery heat exchanger. A high-pressure storage unit coupled to the pump discharge downstream of the recovery heat exchanger.

Abstract: A method for performing an availability measurement on a networked system comprising: identifying at least one measurement point in the system; defining a measurement model configured to return a pass or fail result corresponding to a threshold sensed at the at least one measurement point; measuring the system using the measurement model; populating a table with results from the measurement, the table including rows corresponding to measurement points and columns corresponding to measurement functions for multiple measurements; and aggregating the measurement criteria row results to formulate a single availability value representing the availability of the system.

Abstract: A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.

Abstract: The disclosed device is directed toward a periodic combustion propulsion system. The periodic combustion propulsion system comprises at least one periodic combustion chamber configured to contain periodic combustion and at least one supersonic exhaust nozzle coupled to the at least one periodic combustion chamber. The supersonic exhaust nozzle is configured with a variable exhaust expansion ratio.

Abstract: The present invention provides a computer readable medium containing instructions for generating random jitter test patterns by generating a sequence of maximum-size asynchronous packets according to the P1394b standard and transmitting the sequence to the device under test. The instructions are executed to generate jitter test patterns by disabling the transmitter data scrambler of the second device; clear the port_error register of the device under test; and send a test pattern to said device under test.

Abstract: An inter-tile buffering system for a field programmable gate array (FPGA) comprising a plurality of FPGA tiles arranged in rows and columns. Each tile comprises a plurality of functional and interface groups and a primary routing structure, which is coupled to the functional and interface groups and is configured to receive and route primary output signals within at least one FPGA tile, and provide primary input signals to the functional and interface groups. Each functional group is configured to receive input signals, perform logic operations, and generate output signals and is configured to transfer signals from the routing structure to outside of at least one FPGA tile, and includes a plurality of input multiplexers configured to select signals received from outside at least one FPGA tile and provide signals to the routing structure inside at least one FPGA tile.

Abstract: An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture.

Abstract: A clock tree distribution network for a field programmable gate array comprises an interface with a root signal chosen from at least one of an external clock signal, an internal clock signal, a plurality of phase lock loop cell output signals and programmable elements. The FPGA includes a logic array with programmable elements coupling the logic array to a programmable routing architecture and the interface. A routed clock network selects a signal from a clock signal from the interface, a local signal from the logic array through the routing architecture, Vcc or ground, and routes the selected signal to the logic array through the clock tree distribution network. A hardwired clock network selects a signal from a clock signal from the interface or a local signal from the routing architecture, and routes the selected signal to a plurality of flip-flops in the logic array through the clock tree distribution network.

Abstract: A field effect transistor memory cell has a source region, a drain region, a channel region and a gate region, with the channel region extending from the source region to the drain region and being formed from at least one nanowire which has at least one defect such that charges can be trapped in the defects and released from the defects by a voltage applied to the gate region. A memory device built up from such memory cells and a method of manufacturing such memory cells is also disclosed.

Abstract: Methods are apparatuses are disclosed for library cells for designing an integrated circuit. Various embodiments cover one or more of virtual buses; virtual tap cells; placement primarily for electrical coupling to a well or substrate; placement at a granularity level of electrical coupling to a well or substrate; metal substantially octagonal via structures; free placement according to a minimum drawing resolution of significant features, cell boundary vertices, and routing wires; and cells permitting overlap.

Abstract: A data communications system is disclosed having at least one Legacy cloud coupled to at least one Beta cloud. The system further having at least one BOSS node and at least one border node. A method for ensuring compatibility is disclosed comprising determining when the BOSS node is idle, determining whether the last packet transmitted by any border node was an Alpha format packet if the BOSS node is idle, and unlocking the Legacy cloud if the last packet transmitted by the border node was not an Alpha format packet.

Abstract: A method for generating a substantially sinusoidal waveform containing encoded digital data having one of a first value and a second value at selected phase angles ?n comprises generating the waveform having an amplitude Y defined by a first function at phase angles lying outside of regions having a range ?? beginning at each phase angle ?n, said first function being Y=sin ?; generating the waveform having an amplitude Y defined by the first function at phase angles lying inside the regions having a range of ?? beginning at each phase angle ?n where data of the first value is to be encoded; and generating the waveform having an amplitude Y defined by a second function at phase angles lying inside the regions having a range of ?? associated with each phase angle ?n where data of the second value is to be encoded, the second function being different from Y=sin ?.

Abstract: A snowskateboard includes a support deck having an upper side and a lower side opposite the upper side. First and second trucks are mounted to the lower side. The trucks include rotatable yokes having axles. A set of first runners is disposed over the first yoke axle. A set of second runners is disposed over the second yoke axle. A first biasing mount is mounted in each of the first runners and disposed over the first axle. The first biasing mounts each have first biasing members configured to bias in a torsional direction relative to the first truck axle. A second biasing mount is mounted in each of the second runners and is disposed over the second axle. The second biasing mounts each have second biasing members configured to bias in a torsional direction relative to the second axle.

Abstract: A method and apparatus for call-limiting one or more candidate calls received by a router is disclosed. The method and apparatus may be configured to determine whether ringing one or more candidate calls will exceed a predetermined power limit. If ringing the calls will not exceed said power limit, the calls may be forwarded. If ringing the calls will exceed the power limit, the calls may be placed in a queue.

Abstract: A method and apparatus for assigning an IP address, in a modular network system, to at least one client premise equipment device coupled by a communications link to a router, wherein the last octet of said IP address may be one of at least three different values.