Abstract: An integrated temperature-compensated RC oscillator circuit includes an inverter having an input and an output. An RC network is coupled between the inverter and a pair of comparators. A first comparator has an inverting input coupled to a first reference voltage, a non-inverting input coupled to the RC network, and an output. A second comparator has an inverting input coupled to the RC network, a non-inverting input coupled to a second reference voltage, and an output. A set-reset flip-flop has a set input coupled to the output of the first comparator, a reset input coupled to the output of the second comparator, and an output coupled to the input of the inverter. Differential amplifiers in the comparators each have a diode-connected p-channel MOS transistor controlling a mirrored p-channel MOS transistor whose channel width is less than that of the diode-connected p-channel current mirror transistor.

Abstract: A non-volatile memory configuration scheme is disclosed for volatile-memory-based programmable circuits in a programmable integrated circuit that includes an FPGA fabric, a plurality of first configurable circuit elements external to the FPGA fabric, and a plurality of second configurable circuit elements external to the FPGA fabric. A plurality of distributed configuration non-volatile memory cells is disposed in the FPGA, each one of the distributed configuration non-volatile memory cells coupled to a different one of the plurality of first configurable circuit elements. A non-volatile memory array stores configuration information for the second configurable circuit elements. A plurality of register cells is disposed with the second configurable circuit elements and is coupleable to the non-volatile memory array, each one of the register cells coupled to a different one of the plurality of second configurable circuit elements.

Abstract: An integrated standoff and wall mount apparatus is disclosed. A standoff is formed in the inner surface of a chassis backplane of an electrical device and comprises a conical shape extending generally upward from the inner surface of the chassis backplane. The integrated standoff is used to secure a PCB to the chassis. A keyhole feature may be formed in the surface of both said standoff and said chassis backplane for wall mounting the device. The keyhole feature includes an opening and a groove. A tongue-shaped coverplate is provided that extends from the standoff and provides safety features by covering the keyhole feature. The integrated standoff may be used to wall mount the device using a wall mount fastener secured in the keyhole.

Abstract: The present invention comprises apparatus and a method for simultaneously programming multiple antifuses in a multiple tile field programmable gate array (FPGA). The invention comprises an FPGA having a plurality of logic modules with programmable elements. The logic modules are partitioned into a plurality of individually programmable groups and an isolation device may be coupled between the individually programmable groups of logic modules such that each of the programmable elements in each of the plurality of individually programmable logic modules may be programmed concurrently.

Abstract: An electronic shutter switching transistor for a CMOS electronic is formed in a semiconductor substrate of a first conductivity type. The transistor comprises a pair of spaced apart doped regions of a second conductivity type opposite the first conductivity type disposed in the semiconductor substrate forming source/drain regions. A gate is disposed above and insulated from the semiconductor substrate and is self aligned with the pair of spaced apart doped regions. A well of the second conductivity type laterally surrounds the pair of spaced apart doped regions and extends deeper into the substrate than the doped regions. A buried layer of the second conductivity type underlies and is in contact with the well.

Abstract: A field programmable gate array logic cell includes a logic circuit having three inputs and at least one output and a plurality of multiplexers having inputs and outputs. The logic circuit also includes a plurality of programmable elements coupled between the three inputs and at least one output of the logic circuit and the inputs and outputs of the plurality of multiplexers such that a plurality of sequential logic units and combinatorial units can be realized by programming selected ones of the programmable elements, the sequential logic units may include a flip-flop.

Abstract: A low capacitance measurement probe is disclosed. The low capacitance measurement probe comprises an outer conductor forming an outer wall having an exterior and an interior; a non-conductive spacer forming a first wall having an exterior and an interior with the non-conductive spacer being coupled to the interior of the outer conductor; a conductive layer forming a second wall having an exterior and an interior, the conductive layer coupled to the interior of the first wall; an insulating layer forming a third wall having an exterior and an interior, the insulating layer coupled to the interior of the second wall; and an inner conductor forming an inner wall having an exterior and an interior, the inner conductor coupled to the interior of the third wall. A low capacitance measurement probe system and a method of using a low capacitance measurement probe are also disclosed.

Abstract: A deployable automatic foam fire suppressant system comprising a pump module having at least one pump coupled to a foam material source, the at least one pump comprising a pump suction component for the supply of water, and a supply module configured for coupling to the pump module, the supply module including at least one supply means having fluid conduit and at least one foam applicator. fluidly coupled to the pump module, wherein the pump module and the supply module are deployable and configured to be operated from a remote location.

Abstract: A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A real-time clock is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A programmable logic block is coupled to the clock conditioning circuit and the real-time clock.

Abstract: A field programmable gate array architecture having a plurality of input/output pads comprising: a plurality of logic clusters; a plurality of input/output clusters; a plurality of input/output buffers; a plurality of dedicated input/output first-in/first-out memory blocks, the dedicated input/output first-in/first-out memory blocks having a first-in/first-out memory coupled to one of the plurality of input/output pads; and a routing interconnect architecture programmably coupling the logic clusters, input/output buffers and the input/output clusters, wherein the dedicated input/output first-in/first-out memory blocks are programmably coupled between the input/output buffers and the input/output clusters.

Abstract: A programmable system-on-a-chip integrated circuit device includes a programmable logic block. A digital input/output circuit block is coupled to the programmable logic block. A SRAM block is coupled to the programmable logic block. At least one non-volatile memory block is coupled to the programmable logic block. A JTAG port is coupled to the programmable logic block. An analog circuit block including an analog-to-digital converter may be coupled to the programmable logic block and an analog input/output circuit block may be coupled to the analog circuit block.

Abstract: Tennis balls are propelled to a person practicing the game. The balls are propelled by a head that is vertically repositionable and horizontally aimable. The apparatus includes a main frame, including an attached control box, having a dual hinge; a deformable parallelogram lifting arm, having a first end and a second end, attached at its first end to the dual hinge on the main frame; a movable vertically extending member, rotatably receiving and supported by the second end of the lifting arm at a first end; an oscillating bracket, disposed at a second end having at least one upwardly extending arm, rotatable around a vertical axis; a ball propulsion device mounted on the oscillating bracket to be horizontally rotatable; and a feed support attached to the oscillating bracket above the ball propulsion device providing a source of balls for the ball propulsion device.

Abstract: A multiple memory layer device has a plurality of stacked memory layers. Each of the memory layers has: a charge generating layer of p-type semiconductor material with a plurality of n-type diffusion regions; an insulating layer disposed over the charge generating layer; a charge storing layer disposed over the insulating layer; and another insulating layer disposed over the charge storing layer. A gate is disposed over the top insulting layer in the uppermost memory layer in the plurality of stacked memory layers.

Abstract: First and second complimentary static random-access-memory cell bit lines are coupled to first and second bit nodes through first and second access transistors controlled by a word line. A first inverter has an input coupled to the first bit node and an output coupled to the second bit node. A second inverter has an input coupled to the second bit node and an output coupled to the first bit node through a first transistor switch. A transistor switch is coupled between the output of a non-volatile memory cell and the first bit node. A control circuit coupled to the gate of the transistor switch. Either the drive level of the non-volatile memory cell is selected to overpower the output of the second inverter or the second inverter is decoupled from the first bit node while the output of the non-volatile memory cell is coupled to the first bit node.

Abstract: A method and apparatus for accelerating detection of speed code signals, and in particular S400 signals, for IEEE Standard 1394-1995 serial bus devices. The present invention validates S400 mode immediately after detecting an S400 speed signal, or immediately after detecting an S400 speed signal following a first S200 speed signal. The invention further provides S200 and S100 mode validation according to current implementations. Additionally, the invention does not require RX_DATA_PREFIX as a pre-requisite for signal detection.

Abstract: An operating theater lamp has at least one lamp body with a discharge lamp, which illuminates a site of an operation via optical means. The illuminance of the operating theater lamp can be changed in the region of the site of the operation by a mechanically adjustable diaphragm means. The adjustable diaphram means has adjustable lamellae that extend along a longitudinal axis of at least one discharge lamp. The adjustable lamellae pivot about a longitudinal axis. The adjustable diaghragm means include openings that restrict a maximum dimming effect of the adjustable diaghrahm means.

Abstract: A mounting assembly for sectorized antennas comprising: a plurality of vertical mounting columns, each of said plurality of vertical mounting columns being configured to support an antenna; and a first horizontal bracket having a top surface and a perimeter, said perimeter being defined by an inner portion configured to be secured to a vertical support structure and an outer portion configured to support said plurality of vertical mounting columns, wherein said vertical mounting columns may not be rotated for azimuth adjustment, wherein said inner portion of said first horizontal bracket comprises a V-notch positioned substantially at the center of said inner portion, a first inner vertical surface integral with said first horizontal bracket, and a second inner vertical surface integral with said first horizontal bracket, and wherein said outer portion of said first horizontal bracket comprises at least one outer vertical surface integral with said first horizontal bracket.

Abstract: A current mirror comprising: a first current source; a first n-channel MOS transistor having a drain and a gate coupled to said current source and a source coupled to ground; a second n-channel MOS transistor having a drain, a gate coupled to said drain and said gate of said first n-channel MOS transistor, and a source coupled to ground; a third n-channel MOS transistor having a source coupled to said drain of said second n-channel MOS transistor, a gate, and a drain comprising an output-current node; a second current source; a p-channel MOS transistor having a drain coupled to ground, a source coupled to said second current source and said gate of said third n-channel MOS transistor, and a gate coupled to said drain and said gate of said first n-channel MOS transistor.

Abstract: An optical amplifier is disclosed comprising a signal semiconductor optical amplifier having a waveguide, forming at least part of a signal path between an input and an output, extending along a signal active region for amplification of a signal. The amplifier also includes a control active region of semiconductor material having a gain which is controllable independently from the gain of the signal active region. The amplifier also includes a laser cavity containing both the signal active region and the control active region and being capable of clamping the gain of the signal active region, and the control active region is arranged not to amplify a signal in the signal path within a predetermined signal band.

Abstract: An enhanced virus detection monitoring (VDM) system and method suitable for use with network systems, and in particular electronic document control systems (EDCS) is disclosed. The VDM system intercepts files and documents before they are made available to other users (“check-in”) and inspects the files/documents for virus infection. If a virus infection is found in a file or document, the VDM system invokes anti-virus software to disinfect the file or document. Once the virus has been removed from the file or document, the file (or document) is then made available to other users of the system. If the virus cannot be removed, the file (or document) is not allowed to be checked-in.