Patents Assigned to ATI Technologies ULC
  • Display engine initiated prefetch to system cache to tolerate memory long blackout
    Patent number: 11783799
    Abstract: A disclosed technique includes prefetching display data into a cache memory, wherein the display data includes data to be displayed on a display during a memory black-out period for a memory; triggering the memory black-out period; and during the black-out period, reading from the cache memory to obtain data to be displayed on the display.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: October 10, 2023
    Assignee: ATI Technologies ULC
    Inventors: Tony Chang-Yi Cheng, Oswin Hall
  • Method and apparatus for power management of a graphics processing core in a virtual environment
    Patent number: 11782494
    Abstract: A method and apparatus controls power management of a graphics processing core when multiple virtual machines are allocated to the graphics processing core on a much finer-grain level than conventional systems. In one example, the method and apparatus processes a plurality of virtual machine power control setting requests to determine a power control request for a power management unit of a graphics processing core. The method and apparatus then controls power levels of the graphics processing core with the power management unit based on the determined power control request.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: October 10, 2023
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Oleksandr Khodorkovsky, Stephen D. Presant
  • Pre-display adaptive codeword mapping for display monitor with non-ideal electro-optical transfer function
    Patent number: 11776508
    Abstract: A system includes a display monitor compatible with a video specification having a reference EOTF while exhibiting an actual EOTF that deviates from the reference EOFT. The system further includes a video source subsystem operable to determine an approximated EOTF representative of the actual EOTF based on user input received from a display of at least one test pattern to the user via the display monitor. The at least one test pattern is intended to elicit input from the user based on a visual inspection of the at least one test pattern by the user. The video source subsystem further is to convert color values of each video image of a stream of images to corresponding non-linear codewords based on the approximated EOTF, and transmit the codewords to the display monitor for display as display images representative of the video images.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: October 3, 2023
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Shu Key Keith Lee, David I. J. Glen
  • Reference frame detection using sensor metadata
    Patent number: 11778168
    Abstract: Reference frame detection using sensor metadata, including: storing a plurality of first frames each corresponding to first metadata, wherein the first metadata for each first frame of the plurality of first frames is based on first sensor data from one or more sensors; generating a second frame corresponding to second metadata based on the one or more sensors; identifying, based on the first metadata of the plurality of first frames and the second metadata, a reference frame of the plurality of first frames; and encoding the second frame based on the reference frame.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: October 3, 2023
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Sonu Thomas, Baochun Li, Yang Liu, Ihab Amer
  • Security for microengine access
    Patent number: 11768696
    Abstract: A technique for managing access to a micro engine, the method comprising: determining that a virtual function “VF”) is to be given access to direct communication with a micro engine; in response to the determining, configuring the micro engine to accept direct communication from the VF; monitoring for unpermitted communication; and after a time period has expired, configuring the micro engine to no longer accept direct communication from the VF.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: September 26, 2023
    Assignee: ATI Technologies ULC
    Inventors: Yinan Jiang, Kamraan Nasim, Dezhi Ming, Ahmed M. Abdelkhalek, Dmytro Chenchykov, Andy Sung
  • Low latency long short-term memory inference with sequence interleaving
    Patent number: 11769041
    Abstract: Systems, apparatuses, and methods for implementing a low latency long short-term memory (LSTM) machine learning engine using sequence interleaving techniques are disclosed. A computing system includes at least a host processing unit, a machine learning engine, and a memory. The host processing unit detects a plurality of sequences which will be processed by the machine learning engine. The host processing unit interleaves the sequences into data blocks and stores the data blocks in the memory. When the machine learning engine receives a given data block, the machine learning engine performs, in parallel, a plurality of matrix multiplication operations on the plurality of sequences in the given data block and a plurality of coefficients. Then, the outputs of the matrix multiplication operations are coupled to one or more LSTM layers.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: September 26, 2023
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Sateesh Lagudu, Lei Zhang, Allen H. Rush
  • STACK-BASED RAY TRAVERSAL WITH DYNAMIC MULTIPLE-NODE ITERATIONS
    Publication number: 20230298256
    Abstract: A technique for performing ray tracing operations is provided. The technique includes, in response to detecting that a threshold number of traversal stage work-items of a wavefront have terminated, increasing intersection test parallelization for non-terminated work-items.
    Type: Application
    Filed: June 20, 2022
    Publication date: September 21, 2023
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Daniel James Skinner, Michael John Livesley, David William John Pankratz
  • Glitchless GPU switching at a multiplexer
    Patent number: 11763414
    Abstract: A rendering device signals a display device to capture and replay a current frame to maintain a static image while switching between multiple graphics processing units (GPUs) at a multiplexer (MUX). Replaying the current frame while the MUX switch is in progress smooths the user experience such that no screen blanking or artifacts are observable.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: September 19, 2023
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Anthony W L Koo, Syed Athar Hussain
  • Reduced vertical blanking regions for display systems that support variable refresh rates
    Patent number: 11763778
    Abstract: A graphics processing unit (GPU) includes a timing reference one or more processors configured to generate and provide, based on the timing reference, frames to a display system that supports variable refresh rates. The frames include a vertical blanking region having a first duration. The display system transmits information indicating an operation to be performed by the display system during the vertical blanking region of one or more subsequent frames. The one or more processors are configured to increase the first duration to a second duration in response to receiving the information indicating an operation to be performed by the display system during the vertical blanking region of at least one subsequent frame. In some cases, the first duration of the vertical blanking region is a minimum duration that corresponds to a maximum refresh rate supported by the display system.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: September 19, 2023
    Assignee: ATI TECHNOLOGIES ULC
    Inventor: David I. J. Glen
  • MULTI-THREAD GRAPHICS PROCESSING SYSTEM
    Publication number: 20230289916
    Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.
    Type: Application
    Filed: May 19, 2023
    Publication date: September 14, 2023
    Applicant: ATI Technologies, ULC
    Inventors: Laurent LEFEBVRE, Andrew GRUBER, Stephen MOREIN
  • MEMORY ORGANIZATION FOR MULTI-MODE SUPPORT
    Publication number: 20230280906
    Abstract: A memory package includes first, second, third, and fourth channels arranged consecutively in a clockwise direction on the memory package, each of the first, second, third, and fourth channels having access circuitry and memory arrays. In a first mode, the first channel controls access to the memory arrays in the second channel and the fourth channel controls access to the memory arrays in the third channel.
    Type: Application
    Filed: November 7, 2022
    Publication date: September 7, 2023
    Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Xuan Chen, Ross V. La Fetra, Michael John Litt
  • TECHNIQUE FOR EXTENDED IDLE DURATION FOR DISPLAY TO IMPROVE POWER CONSUMPTION
    Publication number: 20230280819
    Abstract: A method and system for operating in a single display mode operation and a dual pipe mode of operation is disclosed. The method and system includes operating in a dual pipe mode of operation in which each display pipe transmits data from a respective buffer to an associated display. The method and system further includes operating in a single display mode of operation in which one display pipe transmits data from a plurality of buffers to an associated display.
    Type: Application
    Filed: May 12, 2023
    Publication date: September 7, 2023
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Alexander J. Branover, Christopher T. Weaver, Benjamin Tsien, Indrani Paul, Mihir Shaileshbhai Doctor, Thomas J. Gibney, John P. Petry, Dennis Au, Oswin Hall
  • Memory pools in a memory model for a unified computing system
    Patent number: 11741019
    Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a plurality of processors. The method includes receiving a memory operation from a processor that references an address in a shared memory, mapping the received memory operation to at least one virtual memory pool to produce a mapping result, and providing the mapping result to the processor.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: August 29, 2023
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Anthony Asaro, Kevin Normoyle, Mark Hummel
  • Method and apparatus for managing processor functionality
    Patent number: 11740944
    Abstract: A method and apparatus for managing processor functionality includes receiving, by the processor, data relating to one or more environmental conditions. The processor compares the data to pre-existing parameters to determine whether or not the environmental conditions are within the pre-existing parameters for normal operation. If the data are within the pre-existing parameters for normal operation, the processor is operated in a normal operation mode. If the data are outside the pre-existing parameters for normal operation, the processor operates in a second operation mode which is dynamically determined and calibrated during power-on, boot and operation.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: August 29, 2023
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Amitabh Mehra, Anil Harwani, William Robert Alverson, Jerry Anton Ahrens, Jr., Charles Sum Yuen Lee, John William Abshier
  • METHOD AND SYSTEM FOR IMPROVED VISIBILITY IN BLENDED LAYERS FOR HIGH DYNAMIC RANGE DISPLAYS
    Publication number: 20230267581
    Abstract: There are many instances where a standard dynamic range (“SDR”) overlay is displayed over high dynamic range (“HDR”) content on HDR displays. Because the overlay is SDR, the maximum brightness of the overlay is much lower than the maximum brightness of the HDR content, which can lead to the SDR elements being obscured if those elements have at least some transparency. The present disclosure provides techniques including modifying the luminance of either or both of the HDR and SDR content when an SDR layer with some transparency is displayed over HDR content. A variety of techniques are provided. In one example, a fixed adjustment is applied to pixels of one or both of the SDR layer and the HDR layer. The fixed adjustment comprises decreasing the luminance of the HDR layer and/or increasing the luminance of the SDR layer. In another example, a variable adjustment is applied.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 24, 2023
    Applicant: ATI Technologies ULC
    Inventors: Jie Zhou, David I.J. Glen
  • Migrating pages of memory accessible by input-output devices
    Patent number: 11726693
    Abstract: An electronic device includes a memory, an input-output memory management unit (IOMMU), a processor that executes a software entity, and a page migration engine. The software entity and the page migration engine perform operations for preparing to migrate a page of memory that is accessible by the at least one IO device in the memory, the software entity and the page migration engine set migration state information in a page table entry for the page of memory based on the operations being performed. When the operations for preparing to migrate the page of memory are completed, the page migration engine migrates the page of memory in the memory. The IOMMU uses the migration state information in the page table entry to control one or more operations of the IOMMU.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: August 15, 2023
    Assignee: ATI Technologies ULC
    Inventors: Philip Ng, Nippon Raval
  • Method and apparatus for providing a picture-in-picture (PIP) overlay window on a single physical monitor
    Patent number: 11721306
    Abstract: Methods and apparatus provide a picture-in-picture (PIP) overlay window on a single physical monitor by displaying a first swap chain of the single physical monitor, reporting to an operating system (OS), a display level request for a fake connection to a non-existent second monitor, and displaying on the single physical monitor a virtual display defined by a second swap chain of the non-existent second monitor, as the PIP overlay window on the displayed content of the first swap chain on the single physical monitor.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: August 8, 2023
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Nitant Patel, Parimalkumar Patel, Anthony Brown
  • Arbitration Allocating Requests During Backpressure
    Publication number: 20230244623
    Abstract: An arbitration system receives requests to access a destination during an arbitration window that spans multiple processor clock cycles. During each clock cycle, the destination is monitored to determine whether the destination is suffering from backpressure by receiving more requests than the destination is able to accommodate during the clock cycle. In response to detecting backpressure, a masking index value assigned to a requesting source is incremented, which limits an amount of requests from the source that will be granted destination access during a subsequent arbitration window. Alternatively, in response to detecting an absence of backpressure during an arbitration window, the masking index value is decremented, which increases the amount of requests from the source that will be granted destination access during a subsequent arbitration window.
    Type: Application
    Filed: December 8, 2021
    Publication date: August 3, 2023
    Applicant: ATI Technologies ULC
    Inventors: Michael E. McLean, Philip Ng
  • Controlling electrical power consumption for elements in an electronic device based on a platform electrical power limit
    Patent number: 11714442
    Abstract: An electronic device includes an accelerated processing unit (APU) and multiple elements. The APU performs operations for a platform boost and throttle (PBT) controller. For the operations, the APU receives a platform electrical power limit, the platform electrical power limit being a limit on a total electrical power allowed to be consumed by a group of the elements at a given time. The APU then determines a present platform electrical power consumption. The APU next adjusts one or more operating parameters for specified elements from among the group of elements to control electrical power consumption by the specified elements based on a relationship between the present platform electrical power consumption and the platform electrical power limit.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: August 1, 2023
    Assignees: ATI Technologies ULC, Advanced Micro Devices Inc.
    Inventors: Meeta Surendramohan Srivastav, Ashwini Chandrashekhara Holla, Alex Sabino Duenas, Xinzhe Li, Michael John Austin, Indrani Paul, Sriram Sambamurthy
  • Address translation services buffer
    Patent number: 11714766
    Abstract: An address translation buffer or ATB is provided for emulating or implementing the PCIe (Peripheral Component Interface Express) ATS (Address Translation Services) protocol within a PCIe-compliant device. The ATB operates in place of (or in addition to) an address translation cache (ATC), but is implemented in firmware or hardware without requiring the robust set of resources associated with a permanent hardware cache (e.g., circuitry for cache control and lookup). A component of the device (e.g., a DMA engine) requests translation of an untranslated address, via a host input/output memory management unit for example, and the response (including a translated address) is stored in the ATB for use for a single DMA operation (which may involve multiple transactions across the PCIe bus).
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: August 1, 2023
    Assignee: ATI Technologies ULC
    Inventors: Philip Ng, Vinay Patel