Patents Assigned to ATI Technologies ULC
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Patent number: 11605149Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.Type: GrantFiled: March 30, 2022Date of Patent: March 14, 2023Assignee: ATI Technologies ULCInventors: Stephen L. Morein, Laurent Lefebvre, Andrew E. Gruber, Andi Skende
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Publication number: 20230071892Abstract: Systems and methods are disclosed that automatically generating a gameplay recording from an application. Techniques are provided to extract data from a buffer, the extracted data are associated with the application; to detect, based on a signature associated with the extracted data, the occurrence of an event; and upon detection of the occurrence of the event, to generate the gameplay recording from an output of the application.Type: ApplicationFiled: September 3, 2021Publication date: March 9, 2023Applicant: ATI Technologies ULCInventors: Wei Liang, Le Zhang, Ilia Blank, Patrick Pak Kin Fok
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Patent number: 11593311Abstract: An electronic device, including a compression subsystem with a comparator, a history buffer, a match detector, and a command generator, performs operations for generating compressed data from original data. The compression subsystem, starting in each cycle of a clock, processes a search string that is copied from original data to generate commands for compressed data. For processing each search string, the comparator compares each of N substrings from the search string with stored data from the history buffer to find matches between the substrings and the stored data. The match detector then determines a longest match for each of the substrings. The command generator next selectively outputs commands for the compressed data based on the longest matches for the substrings.Type: GrantFiled: September 24, 2019Date of Patent: February 28, 2023Assignee: ATI TECHNOLOGIES ULCInventor: Vinay Patel
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Patent number: 11594194Abstract: A display system supports variable refresh rates that include a plurality of refresh rates. A source such as a graphics processing unit (GPU) provides frames to the display system at a selected one of the refresh rates. The refresh rates are factored into a corresponding plurality of prime factors. A plurality of numbers of lines per frame in frames provided at the plurality of refresh rates is determined based on one or more ratios of the plurality of refresh rates, the plurality of prime factors, and a line rate for providing frames to the display system at the plurality of refresh rates. The source then selectively provides frames to the display system at one refresh rate of the plurality of refresh rates using the same line rate regardless of which refresh rate is chosen. Furthermore, the number of lines per frame is an integer for frames provided at the refresh rates.Type: GrantFiled: September 24, 2020Date of Patent: February 28, 2023Assignee: ATI TECHNOLOGIES ULCInventor: David I.J. Glen
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Patent number: 11586419Abstract: A processing system includes a pseudo-random bit sequence (PRBS) control unit and a PRBS generator that is used to dynamically generate a PRBS from, for example, a first PRBS and a second PRBS. The PRBS generator is coupled to the PRBS control unit. The PRBS generator generates the second PRBS by dynamically adjusting from a first set of flip-flops of a master set of flip-flops that generate the first PRBS to a second set of flip-flops of the first master set of flip-flops that generate the second PRBS. The PRBS generator includes a plurality of PRBS logic engines coupled to a first PRBS multiplexer, the first PRBS multiplexer being used to select either the first PRBS or the second PRBS that is output by the PRBS generator.Type: GrantFiled: September 23, 2020Date of Patent: February 21, 2023Assignee: ATI TECHNOLOGIES ULCInventor: Daniel Harvey McLean
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Patent number: 11579876Abstract: A method of save-restore operations includes monitoring, by a power controller of a parallel processor (such as a graphics processing unit), of a register bus for one or more register write signals. The power controller determines that a register write signal is addressed to a state register that is designated to be saved prior to changing a power state of the parallel processor from a first state to a second state having a lower level of energy usage. The power controller instructs a copy of data corresponding to the state register to be written to a local memory module of the parallel processor. Subsequently, the parallel processor receives a power state change signal and writes state register data saved at the local memory module to an off-chip memory prior to changing the power state of the parallel processor.Type: GrantFiled: August 31, 2020Date of Patent: February 14, 2023Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULCInventors: Anirudh R. Acharya, Alexander Fuad Ashkar, Ashkan Hosseinzadeh Namin
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Patent number: 11575916Abstract: An encoding method is provided which includes receiving a plurality of images, obtaining values of elements in a portion of the images, sorting the elements according to different values of the elements, sorting the elements according to a number of occurrences of the different values and encoding the elements using a subset of the different values having corresponding numbers of occurrences that are higher than corresponding numbers of occurrences of other values. Examples also include a processing device and method for use with palette mode encoding in which the elements are a portion of pixels in images and the values are color values of the portion of pixels in the images.Type: GrantFiled: October 30, 2020Date of Patent: February 7, 2023Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Shu-Hsien Wu, Crystal Yeong-Pian Sau, Yang Liu, Wei Gao, Feng Pan, Ihab M. A. Amer, Ying Luo, Edward A. Harold, Gabor Sines, Ehsan Mirhadi
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Publication number: 20230036191Abstract: A disclosed technique includes transmitting data in a first buffer associated with a first display pipe to a first display associated with the first display pipe; transmitting data in a second buffer associated with a second display pipe to the first display; requesting wake-up of a memory; and refilling one or both of the first buffer and the second buffer from the memory.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Alexander J. Branover, Christopher T. Weaver, Benjamin Tsien, Indrani Paul, Mihir Shaileshbhai Doctor, Thomas J. Gibney, John P. Petry, Dennis Au, Oswin Hall
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Publication number: 20230034633Abstract: A data processor includes a plurality of requestors, a plurality of responders, and a data fabric. The data fabric is for routing requests between the plurality of requestors and the plurality of responders and has a plurality of non-operational power states including a normal C-state and a light-weight C-state. The light-weight C-state has lower entry and exit latencies than the normal C-state. The data fabric monitors traffic through the data fabric and places the data fabric in the light-weight C-state in response to detecting an idle traffic state.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Benjamin Tsien, Alexander J. Branover, Dilip Jha, James R. Magro, MingLiang Lin, Kostantinos Danny Christidis, Hui Zhou
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Patent number: 11568527Abstract: Calculating, for each frame of a plurality of frames, a corresponding quality value; calculating, for each frame of the plurality of frames, based on one or more visual attributes of a frame, a weight for the corresponding quality value of the frame; calculating an aggregate quality value for the plurality of frames based on the weight and the corresponding quality value for each frame of the plurality of frames; and providing an assessment of the plurality of frames based on the aggregate quality value for the plurality of frames.Type: GrantFiled: September 24, 2020Date of Patent: January 31, 2023Assignee: ATI TECHNOLOGIES ULCInventors: Feng Pan, Yang Liu, Crystal Sau, Wei Gao, Mingkai Shao, Dong Liu, Ihab Amer, Gabor Sines
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Patent number: 11567666Abstract: An electronic device includes a memory, a processor that executes a software entity, a page migration engine (PME), and an input-output memory management unit (IOMMU). The software entity and the PME perform operations for preparing to migrate a page of memory that is accessible by at least one IO device in the memory, the software entity and the PME set migration state information in a page table entry for the page of memory and information in reverse map table (RMT) entries involved with migrating the page of memory based on the operations being performed. The IOMMU controls usage of information from the page table entry and controls performance of memory accesses of the page of memory based on the migration state information in the page table entry and information in the RMT entries. When the operations for preparing to migrate the page of memory are completed, the PME migrates the page of memory in the memory.Type: GrantFiled: March 24, 2021Date of Patent: January 31, 2023Assignee: ATI Technologies ULCInventors: Philip Ng, Nippon Raval
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Patent number: 11568248Abstract: A processing device for executing a machine learning neural network operation includes memory and a processor. The processor is configured to receive input data at a layer of the machine learning neural network operation, receive a plurality of sorted filters to be applied to the input data, apply the plurality of sorted filters to the input data to produce a plurality of different feature maps, compress the plurality of different feature maps according to a similarity of the feature maps relative to each other and store the plurality of different feature maps in the memory.Type: GrantFiled: March 31, 2020Date of Patent: January 31, 2023Assignee: ATI Technologies ULCInventors: Arash Hariri, Mehdi Saeedi, Boris Ivanovic, Gabor Sines
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Patent number: 11561797Abstract: An electronic device that includes a decompression engine that includes N decoders and a decompressor decompresses compressed input data that includes N streams of data. Upon receiving a command to decompress compressed input data, the decompression engine causes each of the N decoders to decode a respective one of the N streams from the compressed input data separately and substantially in parallel with others of the N decoders. Each decoder outputs a stream of decoded data of a respective type for generating commands associated with a compression standard for decompressing the compressed input data. The decompressor next generates, from the streams of decoded data output by the N decoders, commands for decompressing the data using the compression standard to recreate the original data. The decompressor next executes the commands to recreate the original data and stores the original data in a memory or provides the original data to another entity.Type: GrantFiled: August 19, 2019Date of Patent: January 24, 2023Assignee: ATI Technologies ULCInventor: Vinay Patel
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Patent number: 11562459Abstract: A graphics pipeline includes a cache having cache lines that are configured to store data used to process frames in a graphics pipeline. The graphics pipeline is implemented using a processor that processes frames for the graphics pipeline using data stored in the cache. The processor processes a first frame and writes back a dirty cache line from the cache to a memory concurrently with processing of the first frame. The dirty cache line is retained in the cache and marked as clean subsequent to being written back to the memory. In some cases, the processor generates a hint that indicates a priority for writing back the dirty cache line based on a read command occupancy at a system memory controller.Type: GrantFiled: December 21, 2020Date of Patent: January 24, 2023Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Noor Mohammed Saleem Bijapur, Ashish Khandelwal, Laurent Lefebvre, Anirudh R. Acharya
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Patent number: 11563945Abstract: A technique for determining an adaptive quantization parameter offset for a block of encoded video includes obtaining a rate control factor for the quantization parameter, determining a content-based quantization parameter factor for the quantization parameter, determining an adaptive variance based quantization offset based on content-based quantization parameter factors for a frame prior to the current frame, and combining the rate control factor, the content-based quantization parameter factor, and the adaptive offset to generate the quantization parameter.Type: GrantFiled: September 30, 2019Date of Patent: January 24, 2023Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Jiao Wang, Ying Zhang, Richard George, Edward A. Harold, Zhenhua Yang
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Patent number: 11557026Abstract: A technique for detecting a glitch in an image is provided. The technique includes providing an image to a plurality of individual classifiers to generate a plurality of individual classifier outputs and providing the plurality of individual classifier outputs to an ensemble classifier to generate a glitch classification.Type: GrantFiled: September 23, 2020Date of Patent: January 17, 2023Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Nicholas Malaya, Max Kiehn, Stanislav Ivashkevich
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Patent number: 11550722Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One system includes a host processor; a memory; a data fabric coupled to the host processor and to the memory; a first input/output memory manage unit (IOMMU) and a second IOMMU, each of the first and second IOMMUs coupled to the data fabric; a first root port and a second root port, each of the first and second root ports coupled to a corresponding IOMMU of the first and second IOMMUs; and a first peripheral component endpoint and a second peripheral component endpoint, each of the first and second peripheral component endpoints coupled to a corresponding root port of the first and second root ports, wherein each of the first and second root ports comprises hardware control logic operative to: synchronize the first and second root ports.Type: GrantFiled: March 2, 2021Date of Patent: January 10, 2023Assignees: ATI TECHNOLOGIES ULC, ADVANCED MICRO DEVICES, INC.Inventors: Philip Ng, Nippon Raval, BuHeng Xu, Rostislav S. Dobrin, Shawn Han
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Patent number: 11551632Abstract: A graphics processing unit (GPU) of a processing system transmits pixel data for a frame to a display in a compressed burst, so that the pixel data is communicated at a rate that is higher than the rate at which the display scans out the pixel data to refresh the frame at a display panel. By transmitting pixel data for the frame in a compressed burst, the GPU shortens the time spent transmitting the pixel data and extends the time before the next frame of pixel data is to be transmitted. During the extended time before the next frame of pixel data is to be transmitted, the GPU saves power by placing portions of the processing system in a reduced power mode.Type: GrantFiled: September 23, 2020Date of Patent: January 10, 2023Assignee: ATI TECHNOLOGIES ULCInventors: Syed Athar Hussain, Anthony W L Koo, David I. J. Glen
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Patent number: 11553222Abstract: Virtual Reality (VR) processing devices and methods are provided for transmitting user feedback information comprising at least one of user position information and user orientation information, receiving encoded audio-video (A/V) data, which is generated based on the transmitted user feedback information, separating the A/V data into video data and audio data corresponding to a portion of a next frame of a sequence of frames of the video data to be displayed, decoding the portion of a next frame of the video data and the corresponding audio data, providing the audio data for aural presentation and controlling the portion of the next frame of the video data to be displayed in synchronization with the corresponding audio data.Type: GrantFiled: December 23, 2020Date of Patent: January 10, 2023Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Lei Zhang, Gabor Sines, Khaled Mammou, David Glen, Layla A. Mah, Rajabali M. Koduri, Bruce Montag
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Patent number: 11551089Abstract: A processing device for executing a machine learning neural network operation includes memory and a processor. The processor is configured to receive input data at a layer of the machine learning neural network operation, receive a plurality of sorted filters to be applied to the input data, apply the plurality of sorted filters to the input data to produce a plurality of different feature maps, compress the plurality of different feature maps according to a sparsity of the feature maps and store the plurality of different feature maps in the memory.Type: GrantFiled: March 31, 2020Date of Patent: January 10, 2023Assignee: ATI Technologies ULCInventors: Mehdi Saeedi, Arash Hariri, Gabor Sines