Patents Assigned to Intel Corporation
  • SELECTIVE PACKING OF PATCHES FOR IMMERSIVE VIDEO
    Publication number: 20240155094
    Abstract: Embodiments are generally directed to selective packing of patches for immersive video. An embodiment of a processing system includes one or more processor cores; and a memory to store data for immersive video, the data including a plurality of patches for multiple projection directions. The system is select the patches for packing, the selection of the patches based at least in part on which of the multiple projection directions is associated with each of the patches. The system is to encode the patches into one or more coded pictures according to the selection of the patches.
    Type: Application
    Filed: November 9, 2023
    Publication date: May 9, 2024
    Applicant: Intel Corporation
    Inventors: Eyal Ruhm, Jill Boyce, Asaf J. Shenberg
  • METHOD AND APPARATUS FOR SHARED VIRTUAL MEMORY TO MANAGE DATA COHERENCY IN A HETEROGENEOUS PROCESSING SYSTEM
    Publication number: 20240152457
    Abstract: Embodiments described herein provide a scalable coherency tracking implementation that utilizes shared virtual memory to manage data coherency. In one embodiment, coherency tracking granularity is reduced relative to existing coherency tracking solutions, with coherency tracking storage memory moved to memory as a page table metadata. For example and in one embodiment, storage for coherency state is moved from dedicated hardware blocks to system memory, effectively providing a directory structure that is limitless in size.
    Type: Application
    Filed: December 6, 2023
    Publication date: May 9, 2024
    Applicant: Intel Corporation
    Inventor: Altug Koker
  • Method and system of image processing of omnidirectional images with a viewpoint shift
    Patent number: 11978177
    Abstract: A method and system of image processing of omnidirectional images with a viewpoint shift.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventors: Radka Tezaur, Niloufar Pourian
  • Machine learning architecture support for block sparsity
    Patent number: 11977600
    Abstract: This disclosure relates matrix operation acceleration for different matrix sparsity patterns. A matrix operation accelerator may be designed to perform matrix operations more efficiently for a first matrix sparsity pattern rather than for a second matrix sparsity pattern. A matrix with the second sparsity pattern may be converted to a matrix with the first sparsity pattern and provided to the matrix operation accelerator. By rearranging the rows and/or columns of the matrix, the sparsity pattern of the matrix may be converted to a sparsity pattern that is suitable for computation with the matrix operation accelerator.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventor: Omid Azizi
  • Offset interposers for large-bottom packages and large-die package-on-package structures
    Patent number: 11978730
    Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventors: Russell K. Mortensen, Robert M. Nickerson, Nicholas R. Watts
  • Glass core patch with in situ fabricated fan-out layer to enable die tiling applications
    Patent number: 11978685
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a glass substrate, with a plurality of first pads on a first surface of the glass substrate, a plurality of second pads on a second surface of the glass substrate that is opposite from the first surface, a plurality of through glass vias (TGVs), wherein each TGV electrically couples a first pad to a second pad, wherein the plurality of first pads have a first pitch, and wherein the plurality of second pads have a second pitch that is greater than the first pitch, a bridge substrate over the glass substrate, a first die electrically coupled to first pads and the bridge substrate, and a second die electrically coupled to first pads and the bridge substrate, wherein the bridge substrate electrically couples the first die to the second die.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventors: Srinivas Pietambaram, Robert L. Sankman, Rahul Manepalli, Gang Duan, Debendra Mallik
  • Continuous learning for object tracking
    Patent number: 11978217
    Abstract: A long-term object tracker employs a continuous learning framework to overcome drift in the tracking position of a tracked object. The continuous learning framework consists of a continuous learning module that accumulates samples of the tracked object to improve the accuracy of object tracking over extended periods of time. The continuous learning module can include a sample pre-processor to refine a location of a candidate object found during object tracking, and a cropper to crop a portion of a frame containing a tracked object as a sample and to insert the sample into a continuous learning database to support future tracking.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventors: Lidan Zhang, Ping Guo, Haibing Ren, Yimin Zhang
  • Detection of listen before talk failure during radio link monitoring
    Patent number: 11979904
    Abstract: Disclosed embodiments are related to distinguishing between listen-before talk (LBT) failure and LBT success, reducing the effect of invalid out-of-sync (OOS) indications and preventing false declaration of radio link failures (RLFs). Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventors: Bishwarup Mondal, Prerana Rane, Yongjun Kwak, Rui Huang
  • Integrated circuits having memory with flexible input-output circuits
    Patent number: 11979152
    Abstract: An integrated circuit may include integrated memory that is formed from a chain of memory blocks. Each memory block may have configurable input and output circuits. The configurable input and output circuits may be interposed between memory circuitry such as a memory array from circuitry external to the memory circuitry. The configurable input and output circuits may have upstream and downstream memory block connection ports. In such a way, configurable input and output circuits in a first memory block may pass control and address signals and data to configurable input and output circuits in a second memory block. By using the configurable input and output circuits, the integrated memory in the integrated circuit may operate to accommodate large bandwidth flows without using the general routing fabric of the integrated circuit.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventors: Chang Kian Tan, Chee Hak Teh
  • Filling openings by combining non-flowable and flowable processes
    Patent number: 11978657
    Abstract: Disclosed herein are methods for manufacturing IC components using bottom-up fill of openings with a dielectric material. In one aspect, an exemplary method includes, first, depositing a solid dielectric liner on the inner surfaces of the openings using a non-flowable process, and subsequently filling the remaining empty volume of the openings with a fill dielectric using a flowable process. Such a combination method may maximize the individual strengths of the non-flowable and flowable processes due to the synergetic effect achieved by their combined use, while reducing their respective drawbacks. Assemblies and devices manufactured using such methods are disclosed as well.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventors: Ebony L. Mays, Bruce J. Tufts
  • Downlink (DL) positioning reference signal (PRS) resource configuration and measurement in new radio (NR) systems
    Patent number: 11979883
    Abstract: Methods, systems, and storage media are described for new radio downlink positioning reference signal (NR DL PRS) resource allocation and configuration. In particular, some embodiments relate to some embodiments relate to NR DL PRS resource configurations such as comb size, number of symbols, DL PRS resource time configuration (e.g., initial start time and periodicity), and providing formulas for calculation of seed for DL PRS sequence generation. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventors: Alexey Khoryaev, Sergey Sosnin, Mikhail Shilov, Sergey Panteleev, Artyom Putilin, Seunghee Han
  • Enhancing performance in network-based systems
    Patent number: 11979301
    Abstract: A method, system, and computer program product, the method comprising: obtaining a data path representing flow of data in processing a service request within a network computing environment having system resources; analyzing the data path to identify usage of the system resources required by the service request processing; determining, based on the usage of the system resources, an optimization action expected to improve the usage of the system resources; and implementing the optimization action in accordance with the data path, thereby modifying operation of the cloud computing environment in handling future service requests.
    Type: Grant
    Filed: April 25, 2021
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventors: Asaf Ezra, Tal Saiag, Ron Gruner
  • Vacuum modulated two phase cooling loop performance enhancement
    Patent number: 11976671
    Abstract: Embodiments disclosed herein include temperature control systems. In an embodiment, a temperature control system comprises a fluid reservoir for holding a fluid, and a spray chamber fluidically coupled to the fluid reservoir. In an embodiment, a pump is between the spray chamber and the fluid reservoir, where the pump provides the fluid to the spray chamber. In an embodiment, the temperature control system further comprises a vacuum source fluidically coupled to the spray chamber, where the vacuum source controls a pressure within the spray chamber, and where the fluid reservoir is between the vacuum source and the spray chamber.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventors: Paul Diglio, Pooya Tadayon, David Shia
  • Cloud-based scale-up system composition
    Patent number: 11977923
    Abstract: Technologies for composing a managed node with multiple processors on multiple compute sleds to cooperatively execute a workload include a memory, one or more processors connected to the memory, and an accelerator. The accelerator further includes a coherence logic unit that is configured to receive a node configuration request to execute a workload. The node configuration request identifies the compute sled and a second compute sled to be included in a managed node. The coherence logic unit is further configured to modify a portion of local working data associated with the workload on the compute sled in the memory with the one or more processors of the compute sled, determine coherence data indicative of the modification made by the one or more processors of the compute sled to the local working data in the memory, and send the coherence data to the second compute sled of the managed node.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventors: Mohan J. Kumar, Murugasamy K. Nachimuthu, Krishna Bhuyan
  • Hierarchical thread scheduling based on multiple barriers
    Patent number: 11977895
    Abstract: Examples described herein relate to a graphics processing unit (GPU) coupled to the memory device, the GPU configured to: execute an instruction thread; determine if a dual directional signal barrier is associated with the instruction thread; and based on clearance of the dual directional signal barrier for a particular signal barrier identifier and a mode of operation, indicate a clearance of the dual directional signal barrier for the mode of operation, wherein the dual directional signal barrier is to provide a single barrier to gate activity of one or more producers based on activity of one or more consumers or gate activity of one or more consumers based on activity of one or more producers.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventors: Sabareesh Ganapathy, Fangwen Fu, Hong Jiang, James Valerio
  • Apparatus, system and method of communicating a multi-link element
    Patent number: 11979925
    Abstract: For example, an apparatus may be configured to generate, transmit, receive and/or process a frame including a multiple Basic Service Set Identifier (BSSID) element corresponding to a multiple BSSID set including a reporting AP, the BSSID element including one or more non-transmitted BSSID profile elements corresponding to one or more other APs belonging to the multiple BSSID set, wherein a non-transmitted BSSID profile element corresponding to an other AP includes one or more elements of information corresponding to the other AP, and a multi-link element, the multi-link element including one or more profile subelements for one or more reported APs of an other MLD including the other AP, respectively, wherein a profile subelement corresponding to a reported AP includes one or more elements of information corresponding to the reported AP.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: May 7, 2024
    Assignee: INTEL CORPORATION
    Inventors: Laurent Cariou, Po-Kai Huang
  • Systems, methods, and apparatuses for tile store
    Patent number: 11977886
    Abstract: Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in at least a form of decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and destination memory information, and execution circuitry to execute the decoded instruction to store each data element of configured rows of the identified source matrix operand to memory based on the destination memory information.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventors: Robert Valentine, Menachem Adelman, Elmoustapha Ould-Ahmed-Vall, Bret L. Toll, Milind B. Girkar, Zeev Sperber, Mark J. Charney, Rinat Rappoport, Jesus Corbal, Stanislav Shwartsman, Igor Yanover, Alexander F. Heinecke, Barukh Ziv, Dan Baum, Yuri Gebil, Raanan Sade
  • PCI configuration and mobility robustness optimization son functionality for 5G networks
    Patent number: 11979943
    Abstract: Systems and methods of re-configuring PCI values for a NR cell and performing mobility robustness optimization are described. To reconfigure the PCI values. The NRM data and the PCI of candidate cells measurements are analyzed to detect a potential PCI collision or PCI confusion among NR cells. In response to detection of the potential PCI collision or confusion, a new PCI value for at least one NR cell is determined and instructions to re-configure the at least one NR cell with the new PCI value are sent to a producer of provisioning MnS. For MRO, a NF provisioning MnS with modifyMOIAttributes operation to configure MRO targets for an MRO function and to enable the MRO function for a NR cell are consumed, as is a performance assurance MnS with a notifyFileReady or reportStreamData operation to collect MRO-related performance measurements. The measurements are analyzed to evaluate MRO performance.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventors: Joey Chou, Yizhi Yao
  • Time encoded data communication protocol, apparatus and method for generating and receiving a data signal
    Patent number: 11979177
    Abstract: An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.
    Type: Grant
    Filed: July 6, 2022
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventors: Elan Banin, Eytan Mann, Rotem Banin, Ronen Gernizky, Ofir Degani, Igal Kushnir, Shahar Porat, Amir Rubin, Vladimir Volokitin, Elinor Kashani, Dmitry Felsenstein, Ayal Eshkoli, Tal Davidson, Eng Hun Ooi, Yossi Tsfati, Ran Shimon
  • Automatic profiling of application workloads in a performance monitoring unit using hardware telemetry
    Patent number: 11977468
    Abstract: A performance monitoring unit of a processor includes one or more performance monitoring counters, and a behavioral detector to sample data from a set of the one or more performance monitoring counters, analyze the sampled data, and identify a type of workload of a software process being executed by the processor.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: May 7, 2024
    Assignee: INTEL CORPORATION
    Inventors: Rahuldeva Ghosh, Zheng Zhang