Abstract: Embodiments are directed to immutable watermarking for authenticating and verifying artificial intelligence (AI)-generated output. An embodiment of a system includes a processor of a monitoring system, wherein the processor is to: receive first content from an edge device and second content from an adversary system, wherein the first content comprises output of a machine learning (ML) model as applied to captured content at the edge device; receive a digital signature corresponding to the first content; process the digital signature to extract a global unique identifier (GUID) of the ML model that generated the first content; verify the extracted GUID against data obtained from a shared registry; in response to successfully verifying the extracted GUID, provide the first content for consumption at a monitoring consumption application; and in response to determining that the second content is not associated with a verifiable GUID, refuse the second content at the monitoring consumption application.

Abstract: Described herein are ferroelectric (FE) memory cells that include transistors having gate stacks separate from FE capacitors of these cells. An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode.

Abstract: Systems and techniques for information centric network (ICN) interworking are described herein. For example, a request may be received at a convergence layer of a node. Here, the request originates from an application on the node. A network protocol, from several available to the node, may be determined to transmit the request. The node then transmits the request via the selected network protocol.

Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

Abstract: Systems and methods for providing a low profile stacked die semiconductor package in which a first semiconductor package is stacked with a second semiconductor package and both semiconductor packages are conductively coupled to an active silicon substrate that communicably couples the first semiconductor package to the second semiconductor package. The first semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a first interconnect pattern having a first interconnect pitch. The second semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a second interconnect pattern having a second pitch that is greater than the first pitch. The second semiconductor package may be stacked on the first semiconductor package and conductively coupled to the active silicon substrate using a plurality of conductive members or a plurality of wirebonds.

Abstract: An apparatus includes a non-planar semiconductor body; and a contact for the semiconductor body. The contact includes an epitaxial material that is formed on and contacts the semiconductor body. The contact includes a second material that is formed on and contacts the epitaxial material; and the second material at least partially conforms to an undercut of the epitaxial material.

Abstract: A disclosed example includes a plurality of display pixels; timing controller circuitry; driver circuitry on a same integrated circuit as the timing controller circuitry, the driver circuitry to drive the display pixels; and de-multiplexer circuitry to de-multiplex pixel data to send to the plurality of display pixels.

Abstract: Digital holographic microscopy and related image processing techniques are described. A hologram captured in an image frame is split into different depths while a new hologram is being captured. Image slices of the hologram are determined and using free space impulse responses that are pre-calculated at a different precision than processing operations using the holographic data. Each computation is calculated in parallel based on the number of available processing cores and threads. The image slices are combined into a 2D array or 3D array to permit further processing of the combined array to count and size particles in the image frame. The reconstructed hologram is displayed at a subsequent image frame than that used to capture the hologram.

Abstract: Gate-all-around integrated circuit structures having germanium nanowire channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium nanowire channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, each of the nanowires including germanium, and the fin including a defect modification layer on a first semiconductor layer, a second semiconductor layer on the defect modification layer, and a third semiconductor layer on the second semiconductor layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

Abstract: Generally discussed herein are systems, devices, and methods that include a communication cavity. According to an example a device can include substrate with a first cavity formed therein, first and second antennas exposed in and enclosed by the cavity, and an interconnect structure formed in the substrate, the interconnect structure including alternating conductive material layers and inter-layer dielectric layers.

Abstract: Various embodiments herein include techniques to indicate a reference subcarrier spacing (SCS) in a soft resource availability configuration for an integrated access and backhaul (IAB) distributed unit (DU)/mobile terminal (MT). For example, the reference SCS may be included in soft resource availability radio resource control (RRC) configuration AvailabilityCombinationsPerCell. Additionally, embodiments include mechanisms for dynamic soft availability indication with paired spectrum operation (e.g., frequency division duplex (FDD) operation). Other embodiments may be described and claimed.

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) for software defined silicon guardianship are disclosed.

Abstract: An apparatus to facilitate inferred object shading is disclosed. The apparatus comprises one or more processors to receive rasterized pixel data and hierarchical data associated with one or more objects and perform an inferred shading operation on the rasterized pixel data, including using one or more trained neural networks to perform texture and lighting on the rasterized pixel data to generate a pixel output, wherein the one or more trained neural networks uses the hierarchical data to learn a three-dimensional (3D) geometry, latent space and representation of the one or more objects.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that implement an automatically evolving code recommendation engine. In one example, the apparatus collects a user code snippet. The apparatus then determines a structured representation of the user code snippet. Next, the apparatus generates a recommended code snippet using the structured representation of the user code snippet. Then the apparatus obtains user-determined code snippet feedback comparing the user code snippet to the recommended code snippet, the user-determined code snippet feedback indicating one of a match, no match, or uncertain. Finally, the apparatus stores a code snippet training pair in a training database, the code snippet training pair including the user code snippet and the recommended code snippet.

Abstract: A thin-film transistor includes a gate electrode, a gate dielectric on the gate electrode, a first layer including a source region, a drain region, and a semiconductor region above and in direct contact with the gate dielectric and physically connecting the source and drain regions, and a second layer including an insulator material on the semiconductor region. The semiconductor region has less vertical thickness than the source and drain regions. In an embodiment, the thickness of the semiconductor region is no more than half that of the source and drain regions. In another embodiment, the second layer physically connects and electrically separates the source and drain regions. In yet another embodiment, a memory cell includes this transistor and a capacitor electrically connected to the drain region, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline.

Abstract: An apparatus to facilitate utilizing structured sparsity in systolic arrays is disclosed. The apparatus includes a processor comprising a systolic array to receive data from a plurality of source registers, the data comprising unpacked source data, structured source data that is packed based on sparsity, and metadata corresponding to the structured source data; identify portions of the unpacked source data to multiply with the structured source data, the portions of the unpacked source data identified based on the metadata; and output, to a destination register, a result of multiplication of the portions of the unpacked source data and the structured source data.

Abstract: Magnetoelectric magnetic tunnel junction (MEMTJ) logic devices comprise a magnetoelectric switching capacitor coupled to a pair of magnetic tunnel junctions (MTJs) by a conductive layer. The logic state of the MEMTJ is represented by the magnetization orientation of the ferromagnetic layer of the magnetoelectric capacitor, which can be switched through the application of an appropriate input voltage to the MEMTJ. The magnetization orientation of the magnetoelectric capacitor ferromagnetic layer is read out by the MTJs. The conductive layer is positioned between the capacitor and the MTJs. The MTJ ferromagnetic free layers are exchange coupled to the ferromagnetic layer of the magnetoelectric capacitor. The potential of an MTJ free layer is based on a supply voltage applied to the reference layer of the MTJ. The MTJ reference layers have a magnetization orientation that is parallel or antiparallel to the magnetization orientations of the ferromagnetic layer of the magnetoelectric capacitor.

Abstract: Moisture hermetic guard ring structures for semiconductor devices, related systems, and methods of fabrication are disclosed. Such devices systems, and methods include a guard ring structure laterally surrounding semiconductor devices of a device layer and metal interconnects of an interconnect layer, the guard ring structure extending through the interconnect layer, the device layer, and a bonding layer adjacent one of the interconnect layer or the device layer the bonding layer, and contacting a support substrate coupled to the bonding layer. Such devices systems, and methods may further include via structures having the same material system as the guard ring structure and also extending through the interconnect, the device, and bonding layers and contacting a support substrate.

Abstract: An integrated circuit structure includes a device layer including a first set of devices and a second set of devices. An interconnect layer is above the device layer, where the interconnect layer includes one or more conductive interconnect features within dielectric material. In an example, a first ring structure including conductive material extends within the interconnect layer, and a second ring structure including conductive material extends within the interconnect layer. In an example, the second ring structure is non-overlapping with the first ring structure. In an example, the first ring structure is above the first set of devices of the device layer, and the second ring structure is above the second set of devices of the device layer.

Abstract: Deep learning models, such as diffusion models, can synthesize images from noise. Diffusion models implement a complex denoising process involving many denoising operations. It can be a challenge to understand the mechanics of diffusion models. To better understand how and when structure is formed, saliency maps and concept formation intensity can be extracted from the sampling network of a diffusion model. Using the input map and the output map of a given denoising operation in a sampling network, a noise gradient map representative of the predicted noise of a given denoising operation can be determined. The noise gradient maps from the denoising operations at different indices can be combined to generate a saliency map. A concept formation intensity value can be determined from a noise gradient map. Concept formation intensity values from the denoising operations at different indices can be plotted.