Abstract: A microelectronic device may include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures, the stack structure divided into block portions. The microelectronic device may additionally include slit structures horizontally interposed between the block portions of the stack structure. Each of the slit structures may include a dielectric liner covering side surfaces of the stack structure and an upper surface of an additional structure underlying the stack structure, and a plug structure comprising at least one metal surrounded by the dielectric liner.

Abstract: An apparatus includes a semiconductor substrate; a line-shaped trench in the semiconductor substrate, an inner wall of the line-shaped trench being covered with an insulating film; a first conductive member including first and second line-shaped portions, the first line-shaped portion filling a lower portion of the line-shaped trench; and line-shaped second and third conductive members extending along the inner wall of the line-shaped trench and facing each other, the line-shaped second and third conductive members having a void therebetween; wherein the second line-shaped portion of the first conductive member protrudes from a central portion of the first line-shaped portion to fill the void.

Abstract: Devices and techniques for packet arbitration for buffered packets in a network device are described herein. A packet can be received at an input of the network device. The packet can be placed in a buffer for the input and a characteristic of the packet can be obtained. A record for the packet, that includes the characteristic, is written into a data structure that is independent of the buffer. Arbitration, based on the characteristic of the packet in the record, can then be performed among multiple packets to select a next packet from the buffer for delivery to an output.

Abstract: The present disclosure includes secure device coupling. An embodiment includes a processing resource, memory, and a network management device communication component configured to, identifying a network attached device within a first domain. Generating a domain device secret corresponding to the first domain. Each network attached device within the first domain can share the same domain device secret. Coupling iterations may be performed for each device within the first domain can include: generating a network management device private key and public key. Providing, via short-range communication, the network management device public key and the domain device secret to a network attached device communication component included in each network attached device of the first domain.

Abstract: Some embodiments include apparatuses and methods of forming the apparatus. One of the apparatuses and methods includes a memory cell having a first transistor and a second transistor located over a substrate. The first transistor includes a channel region. The second transistor includes a channel region located over the channel region of the first transistor and electrically separated from the first channel region. The memory cell includes a memory element located on at least one side of the channel region of the first transistor. The memory element is electrically separated from the channel region of the first transistor, and electrically coupled to the channel of the second transistor.

Abstract: A processing device in a memory sub-system identifies a first memory device and a second memory device and configures the second memory device with a zone namespace. The processing device identifies a first portion and a second portion of the first memory device, the first portion storing zone namespace metadata corresponding to the zone namespace on the second memory device. The processing device further exposes the second portion of the first memory device to a host system as a non-zoned addressable memory region.

Abstract: A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: allocate a named portion of the non-volatile storage device; generate, according to a first block size, first block-wise mapping data; translate, using the first block-wise mapping data, logical addresses defined in the named portion to logical addresses defined for the entire non-volatile storage media, which can then be further translated to physical addresses in a same way for all named portions; determine a second block size; generate, according to the second block size, second block-wise mapping data; translate, using the second block-wise mapping data, the logical addresses defined in the named portion to the logical addresses defined for the entire non-volatile storage media.

Abstract: The address of victim rows may be determined based on rows that are accessed in a memory. The victim addresses may be stored and associated with a count for every time a victim row is “victimized.” When the count for a victim row reaches a threshold, the victim row may be refreshed to preserve data stored in the row. After the victim row has been refreshed, the count may be reset. When a victim row is accessed, the count may also be reset. The counts may be adjusted for closer victim rows (e.g., +/?1) at a faster rate than counts for more distant victim rows (e.g., +/?2). This may cause closer victim rows to be refreshed at a higher rate than more distant victim rows.

Abstract: The present disclosure includes apparatuses and methods related to a memory expansion card suitable for, relative to other memory solutions, a high-speed interface and low power consumption. The memory expansion card can have on-die error correction code (ECC) circuitry and, in some examples, additional on-board circuitry, components, or capability to manage, relative to other memory solutions, a large number of volatile or non-volatile memory devices. A memory expansion card may have a controller with a host interface capable of using or defined according to a quantity of bits (i.e., a bit width), which may be eight bits. The controller may coupled to memory devices via several channels, and each channel may have the bit width of the interface.

Abstract: Methods, systems, and devices for an interactive environmental control system are described. In some examples, operating temperatures for individual zones of an environment may be determined based on inputs received from occupants of the respective zones. For example, a building may be separated into zones, and environmental conditions at each zone may be monitored and adjusted independently. Each occupant of a zone may update their environmental preference and the system may utilize the user inputs to set and adjust an operating temperature for the respective zone based on the occupants' preferences. In some examples, the system may implement machine learning techniques to predict and set operating conditions for the zones based on inputs, such as a history of inputs, from building occupants (e.g., from occupants of a respective zone).

Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line has left and right portions. Spike current suppression is implemented by charge screening structures. The charge screening structures are formed by laterally integrating insulating layers into selected interior regions of the left and/or right portions of the access line. The insulating layers vertically separate the access line into top and bottom conductive portions above and below the insulating layers. For memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the top or bottom conductive portion.

Abstract: The present disclosure is directed to logic based read sample offset operations in a memory sub-system. A processing device performs a first read, a second read, and a third read of data from a memory devices using a first center value corresponding to a first read level threshold, a negative offset value, and a positive offset value, respectively. The processing device performs a XOR operation on results from the first and second reads to obtain a first value and a XOR operation on results from the second and third reads to obtain a second value. The processing device performs a first count operation on the first value to determine a first difference bit count and a second count operation on the second value to determine a second difference bit count. The processing device can store or output the first difference bit count and the second difference bit count.

Abstract: Methods, systems, and devices for hardware reset management for universal flash storage (UFS) are described. A UFS device may initiate a boot-up procedure that includes multiple phases. The UFS device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. The UFS device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. The UFS device may receive the second reset command during the second phase after initiating the portion of the second reset operation. The UFS device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.

Abstract: The disclosed embodiments are directed to improving the persistence of pre-accident data in vehicles. In one embodiment a method is disclosed comprising receiving events broadcast over a vehicle bus; classifying the events using a machine learning model, the classifying comprising indicating that a collision is imminent; and copying data from a cyclic buffer of a black box device into a long-term storage device in response to the classifying.

Abstract: A method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.

Abstract: Methods, systems, and devices for host recovery for a stuck condition of a memory system are described. The host system may transmit a first command for the memory system to transition from a first power mode to a second power mode (e.g., low-power mode). In some cases, the host system may transmit a second command for the memory system to exit the second power mode shortly after transmitting the first command. The host system may activate a timer associated with a time-out condition for exiting the second power mode and may determine that a duration indicated by the timer expires. In some examples, the host system may transmit a third command for the memory system to perform a hardware reset operation based on determining that the duration of the timer expires.

Abstract: Apparatuses and methods can be related to implementing a transformer neural network in a memory. A transformer neural network can be implemented utilizing a resistive memory array. The memory array can comprise programmable memory cells that can be programed and used to store weights of the transformer neural network and perform operations consistent with the transformer neural network.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for soft post-package repair (SPPR). After packaging, it may be necessary to perform post-package repair operations on rows of the memory. During a scan mode of an SPPR operation, addresses provided by a fuse bank may be examined to determine if they are open addresses or if the bad row of memory is a redundant row of memory. The open addresses and the bad redundant addresses may be stored in volatile storage elements, such as in latch circuits. During a soft send mode of a SPPR operation, the address previously associated with the bad row of memory may be associated with the open address instead, and the address of the bad redundant row may be disabled.

Abstract: Methods, systems, and devices for techniques for detecting a state of a bus are described. A memory device may receive an access command transmitted to the memory device via a bus. The memory device may transmit data requested by the access command over data lines and a control signal that indicates the bus is in an active state over a control line. The control signal may be transmitted during a first unit interval of a read operation. The control signal may be configured to have a first voltage when the bus is in an idle state and a second voltage when the bus is in the active state. The control line may be configured to have or trend toward the first voltage when the bus is in the idle state.

Abstract: A memory device to perform a read disturb mitigation operation. For example, the memory device can measure signal and noise characteristics of a group of memory cells to determine an optimized read voltage of the group of memory cells and determine a margin of read disturb accumulated in the group of memory cells. Subsequently, the memory device can identify the group of memory cells for the read disturb mitigation operation based on the margin of read disturb and a predetermined threshold.