Abstract: Methods, systems, and devices for payload validation for a memory system are described. A payload receiver may be a device that includes an array of memory cells configured to store data, and a payload transmitter may be a host of a payload receiver (e.g., a host device) or another device that is in communication with the payload receiver. A payload receiver may be configured to receive an information payload and a signature associated with the information payload. The received signature may be based on the information payload and an identifier of the payload receiver previously provided to the payload transmitter. The payload receiver may generate a signature based on the information payload and the identifier of the payload receiver (e.g., as stored or cached at the payload receiver), and authenticate the information payload based on the received signature and the generated signature.

Abstract: A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: store a namespace map to map blocks of logical addresses defined in a namespace to first blocks of logical addresses defined in a capacity of the non-volatile storage media; without changing a size of the namespace, adjust the namespace map to map the blocks of the logical addresses defined in the namespace to second blocks of the logical addresses defined in the capacity of the non-volatile storage media (e.g., to consolidate blocks for performance improvement); and translate the logical addresses in the namespace to physical addresses for the non-volatile storage media using the namespace map.

Abstract: A memory array comprising laterally-spaced memory blocks individually comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The laterally-spaced memory blocks in a lower one of the conductive tiers comprises elemental-form metal that extends longitudinally-along the laterally-spaced memory blocks proximate laterally-outer sides of the laterally-spaced memory blocks. A metal silicide or a metal-germanium compound is directly against laterally-inner sides of the elemental-form metal in the lower conductive tier and that extends longitudinally-along the laterally-spaced memory blocks in the lower conductive tier. The metal of the metal silicide or of the metal-germanium compound is the same as that of the elemental-form metal. Other embodiments, including method, are disclosed.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described in which waterfall attacks can be prevented from degrading data by alerting a memory controller that the memory device requests time to perform internal management operations, and should not be sent any further commands (e.g., activate commands) for a predetermined amount of time. In one embodiment, a memory device includes an external pin, a mode register, a memory array including a plurality of rows of memory cells, and circuitry configured to: determine that a criterion to perform an internal management operation on a subset of the plurality of rows has been met, transmit, in response to determining the criterion has been met, a signal to the external pin, determine a duration corresponding to the internal management operation, and write a bit value indicative of the determined duration to the mode register.

Abstract: Apparatuses, systems, and methods for direct refresh management (DRFM) sampling protection. A memory receives a DRFM address and DRFM sampling command from a controller. The memory also samples addresses into an aggressor register. Responsive to receiving the DRFM address, the memory may prevent addresses which match the DRFM address from being added to the aggressor register for at least a period of time. For example, a protect flag may be activated for the period of time. If the aggressor register already contained an address which matched the DRFM address, it may be removed.

Abstract: The present disclosure describes a memory device comprising memory cells at cross points of access lines of a memory array, and a two-transistor driver comprising a P-type transistor and a N-type transistor connected to the P-type transistor, the two-transistor driver being configured to drive an access line of the memory array to a discharging voltage during an IDLE phase, to drive said access line to a floating voltage during an ACTIVE phase, and to drive said access line at least to a first or second read/program voltage during a PULSE phase.

Abstract: A cache memory having a memory media device row activation-biased caching policy is described. The cache policies that are biased based on row activation counts include at least one of a cache line eviction policy which determines which cache lines are the most evictable from the cache memory, and cache line storage policy which determined which row data is allocated cache lines for storage. A memory controller including a row activation-biased cache memory is also described. The memory media device may be DRAM.

Abstract: An apparatus that includes first, second, third and fourth circuit regions arranged in a first direction in numerical order. The first circuit region includes a first global power supply line extending in a second direction vertical to the first direction and a first local power supply line, the first local power supply line being branched from the first global power supply line and extending in the first direction across the second, third and fourth regions. The third circuit region includes a first power switch coupled between the first local power supply line and an internal power supply line extending in the first direction across the first, second, third and fourth regions. Each of the second and fourth regions includes a circuit coupled to the first local power supply line and an additional circuit coupled to the internal power supply line.

Abstract: A method used in forming memory circuitry comprises forming transistors individually comprising one source/drain region and another source/drain region. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. Openings are formed through insulative material that is directly above the transistors and into the another source/drain regions. Individual of the openings are directly above individual of the another source/drain regions. A laterally-outer insulator material is formed in the individual openings within and below the insulative material. A laterally-inner insulator material is formed in the individual openings within and below the insulative material laterally-over the laterally-outer insulator material. The laterally-outer insulator material and the laterally-inner insulator material are directly against one another and have an interface there-between.

Abstract: Described apparatuses and methods provide system error correction code (ECC) circuitry routing that segregates even sense amp (SA) line data sets and odd SA line data sets in a memory, such as a low-power dynamic random-access memory. A memory device may include one or more dies, and a die can have even SA line data sets and odd SA line data sets. The memory device may also include ECC circuitry comprising one or more ECC engines. By segregating the data sets, instead of coupling even and odd SA line data sets to a single ECC engine, double-bit errors on a single word line may be separated into two single-bit errors. Thus, by utilizing system ECC circuitry routing in this way, even a one-bit ECC algorithm may be used to correct double bits, which may increase data reliability.

Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

Abstract: An apparatus includes: a first semiconductor substrate; a plurality of first regions extending in parallel in a first direction on the first semiconductor substrate, each of the plurality of first regions including a plurality of first shallow trench isolations (STI) therein; and a plurality of second regions each extending between corresponding adjacent two of the plurality of first regions, each of the plurality of second regions including a plurality of second STIs and a plurality of active regions arranged alternately and in line in the first direction. Each of the plurality of second STIs has a greater depth than each of the plurality of first STIs.

Abstract: Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a flight of stairs. The stairs individually comprise a tread comprising conducting material of one of the conductive tiers. A conductive-via construction extends downwardly from and directly below the conducting material of individual of the treads to circuitry that is directly below the stack. The conductive-via construction comprises an insulator lining circumferentially about conductor material. The insulator lining and the conductor material extend downwardly from the individual treads through that portion of the stack that is directly thereunder.

Abstract: Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.

Abstract: Described apparatuses and methods relate to adaptive refresh staggering for a memory system that may support a nondeterministic protocol. To help manage power-delivery networks in a memory system, a memory device can include logic that can be programmed to stagger the start of refresh operations for each die upon receiving a command to enter a lower-power mode, such as self-refresh. The staggered start can be implemented at a channel level, a package level, or both. The programming sets a delay for each die so that initiation of refresh operations is staggered. Thus, a first die can initiate refresh operations when a command to enter the lower-power mode is received (e.g., approximately zero delay). However, initiation of refresh operations for subsequent dies (e.g., “after” the first die) is delayed, which can reduce peak current draw and power consumption.

Abstract: Apparatuses and methods can be related to implementing adjustable data protection schemes using artificial intelligence. Implementing adjustable data protection schemes can include receiving failure data for the plurality of memory devices and receiving an indication of a failure of a stripe of the plurality of memory devices based on the failure data. Based on failure data, and the indication of the failure of the stripe of the plurality of memory devices, a data protection scheme adjustment can be generated for the memory device. The data protection scheme adjustment can be received from the AI accelerator and can be implemented by a plurality of memory devices.

Abstract: A production host can learn the production state awareness (PSA) modes supported by a memory device and select a particular of one of the supported PSA modes. The memory device can receive host image data from the production host and write the host image data according to the selected PSA mode. The memory device can set a PSA state to load complete after writing the host image data. The memory device can thereby be better situated for being soldered to a memory sub-system.

Abstract: Disclosed in some examples are systems, methods, devices, and machine-readable mediums to detect and terminate programmable atomic transactions that are stuck in an infinite loop. In order to detect and terminate these transactions, the programmable atomic unit may use an instruction counter that increments each time an instruction is executed during execution of a programmable atomic transaction. If the instruction counter meets or exceeds a threshold instruction execution limit without reaching the termination instruction, the programmable atomic transaction may be terminated, all resources used (e.g., memory locks) may be freed, and a response may be sent to a calling processor.

Abstract: Methods, systems, and devices for centralized error correction circuit are described. An apparatus may include a non-volatile memory disposed on a first die and a volatile memory disposed on a second die (different than the first die). The apparatus may also include an interface controller disposed on a third die (different than the first die and the second die). The interface controller may be coupled with the non-volatile memory and the volatile memory and may include an error correction circuit that is configured to operate on one or more codewords received from the volatile memory.

Abstract: Methods, systems, and devices for temperature exception tracking in a temperature log for a memory system are described. The memory system may store the temperature log separate from data to which the temperature information corresponds. For example, a memory device may store data in a relatively higher-level cell and the corresponding temperature information in a relatively lower-level cell. To perform a write operation, the memory system may determine a current temperature at which the data is being written or was written to a partition of a memory device and may indicate in the temperature log if the current temperature is entering a temperature range that is outside a threshold temperature (e.g., a nominal temperature). To perform a read operation, the memory system may determine if the data to read was written to the memory device outside the threshold temperature to determine whether to perform temperature compensation for the read operation.