Abstract: Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.

Abstract: Methods, systems, and devices for in-memory associative processing for vectors are described. A device may perform a computational operation on a first set of contiguous bits of a first vector and a first set of contiguous bits of a second vector. The first sets of contiguous bits may be stored in a first plane of a memory die and the computational operation may be based on a truth table for the computational operation. The device may perform a second computational operation on a second set of contiguous bits of the first vector and a second set of contiguous bits of the second vector. The second sets of contiguous bits may be stored in a second plane of the memory die and the computational operation based on the truth table for the computational operation.

Abstract: Methods, apparatuses and systems related to managing deck-specific read levels are described. The apparatus may include a memory array having the memory cells organized into two or more decks. The apparatus can determine a delay between programming the decks. The apparatus can derive and implement the deck-specific read levels by selectively adjusting a base read level with an offset level according to the delay and/or the targeted read location.

Abstract: Methods, systems, and devices for techniques for managed NAND translation with embedded memory systems are described. A host system may generate a first command to access a logical memory address associated with a memory system. The host system may identify a physical memory address of the memory system based on generating the first command. The host system may output to the memory system a second command and the physical memory address, where the second command may be communicated to the memory device using a protocol associated with a controller of the memory system. The memory system may then access memory cells in a memory device associated with the physical memory address based on receiving the second command and the physical memory address.

Abstract: A timing of an execution of a command in a memory device can be affected delay elements. The delay elements of a unit of delay elements can cause variable delays of the command paths. The delay elements can be activated based on settings stored in a fuse array of a memory device. The delay elements can be used to change a timing of current draw of the memory devices.

Abstract: Implementations described herein relate to burst data read storage. In some implementations, a controller may receive a write command. The controller may determine whether a burst read flag, included in the write command, is set. The controller may write host data, associated with the write command, to a first type of storage block of the memory device or to a second type of storage block of the memory device based on whether the burst read flag is set.

Abstract: An example method of performing read operation with respect to a memory device comprises: receiving a request to perform a read operation with respect to a memory page of a memory device; identifying a block family associated with a block comprising the memory page; determining a block family-based read voltage level associated with the block family; performing, using the block family-based read voltage level, a read operation with respect to the memory page; determining, by performing an error correction operation with respect to the memory page, a new read voltage level associated with the block family; and associating, by a last successful read voltage level memory data structure, the new read voltage level as a last the successful read voltage level with the block family.

Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first and second block and a first and second user data portion are directed to the first and second block. Temporary parity data is generated using the first and second user data portions. The temporary parity data and the first and second user data portions are stored in a buffer. Portions of the first and second block are programmed with two programming passes. The first and second user data portions in the buffer are invalidated in response to a completion of the second programming pass of the portions of the first and second blocks. The temporary parity data is maintained in the buffer until a second programming pass of the first and second block.

Abstract: Implementations described herein relate to memory device operations for unaligned write operations. In some implementations, a memory device may receive, from a host device, a write command indicating data having a first size that corresponds to a first write unit and a first logical address. The memory device may allocate a set of buffers for the write command. The memory device may determine a set of physical addresses corresponding to a physical address that is associated with the second size, where the set of physical addresses are each associated with the first size. The memory device may merge stored data from the set of physical addresses to one or more buffers, from the set of buffers, that do not include the data to generate a data unit having the second size. The memory device may write the data unit to memory indicated by the set of physical addresses.

Abstract: Provided is a computing system including a memory system in communication with a host, to store data therein. The memory system includes a memory having a plurality of memory components coupled to the controller via a memory interface; and a memory controller configured to communicate with the memory to control data transmission and performing scrubbing operation of the memory components and detecting a region of the memory to be sanitized and performing a sanitization operation of the detected region to prevent the occurrence of failure.

Abstract: A memory system includes a memory device comprising a content addressable memory (CAM) block storing a plurality of stored search keys and a value data block. The memory system further includes a processing device that receives an input search key and identifies one of the plurality of stored search keys that matches the input search key, the one of the plurality of stored search keys having an associated match location in the CAM block. The processing device further determines, using the associated match location, a corresponding value location in the value data block and retrieves, from the value location in the value data block, data representing a value associated with the input search key.

Abstract: Methods, systems, and devices for techniques for retiring blocks of a memory system are described. In some examples, aspects of a memory system or memory device may be configured to determine an error for a block of memory cells. Upon determining the occurrence of the error, the memory system may identify one or more operating conditions associated with the block. For example, the memory system may determine a temperature of the block, a cycle count of the block, a quantity of times the block has experienced an error, a bit error rate of the block, and/or a quantity of available blocks in the associated system. Depending on whether a criteria associated with a respective operating condition is satisfied, the block may be enabled or retired.

Abstract: Systems, apparatuses, and methods related to channel architecture for memory devices are described. Various applications can access data from a memory device via a plurality of channels. The channels can be selectively enabled or disabled based on the behavior of the applications. For instance, an apparatus in the form of a memory system can include an interface coupled to a controller and a plurality of channels. The controller can be configured to determine an aggregate amount of bandwidth used by a plurality of applications accessing data from a memory device coupled to the controller via the plurality of channels and disable one or more channels of the plurality of channels based, at least in part, on the aggregate amount of bandwidth used by the plurality of applications.

Abstract: A microelectronic device comprises a conductive line and a transistor adjacent to the conductive line. The transistor comprises a channel material extending into the conductive line, the channel material contacting the conductive line in three dimensions, a dielectric material adjacent to the channel material, a conductive material adjacent to the dielectric material, and a passivation material adjacent to the channel material. The microelectronic device further comprises a conductive contact adjacent to the channel material, the conductive contact including a portion extending between opposing portions of the channel material. Related microelectronic devices, electronic devices, and related methods are also disclosed.

Abstract: An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag, and improves blue response in imaging devices.

Abstract: A memory device includes a memory array comprising a plurality of wordlines and a regulator circuit selectively coupled to the plurality of wordlines, wherein the regulator circuit is configured to perform a detection routine to sample a load current from a selected wordline of the plurality of wordlines and generate a measured output voltage, wherein the measured output voltage modulates with respect to the load current. The memory device further includes a comparator circuit coupled to the regulator circuit, wherein the comparator circuit is configured to generate a comparison result based on a difference between the measured output voltage and a reference voltage and a local media controller coupled to the comparator circuit, wherein the local media controller is configured to identify a presence of a defect on the selected wordline in response to the comparison result satisfying a threshold condition.

Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a vertical three-dimensional cross-point memory device uses digit line decoders that include, on the digit line side of memory cells, a current limiter and sensing circuit configured to control program current in either of positive or negative program polarities, as selected by a controller. Two current limiters are each used on the digit line side of each memory cell. A negative polarity current limiter is used for pull-up, and a positive polarity current limiter is used for pull-down. A negative polarity sensing circuit is used between the respective digit line decoder and a positive supply voltage. A positive polarity sensing circuit is used between the respective digit line decoder and a negative supply voltage. The current limiter and sensing circuit pair of the same polarity is coupled to each digit line decoder based on the selected program polarity.

Abstract: Components of sense amplifiers may share contacts that couple the components to a global line via a local line. In some examples, the components may be pull-down circuits of a same sense amplifier or pull-down circuits of adjacent sense amplifiers. The shared contact may include a transistor or a resistance between the local line and the global line. In some examples, the global line may be an RNL line. The transistor or resistance may reduce the impact of voltage across the components from affecting the global line and/or reduce the impact of voltage changes on the global line on the individual components.

Abstract: Methods, systems, and devices for managing memory based on access duration are described. A memory device may include a first set of memory cells resilient against access durations of a first duration and a second set of memory cells resilient against access durations of a shorter duration. A command for accessing the memory device may be received. The command may be associated with an access duration. Whether to access, as part of executing the command, the first set of memory cells or the second set of memory cells may be determined based on the access duration. The first set of memory cells may be accessed, as part of executing the command, based on the access duration being greater than a threshold duration. Or the second set of memory cells may be accessed based on the access duration being less than or equal to the threshold duration.

Abstract: Bake temperatures for memory blocks can be determined as part of an operation to allocate memory blocks for us by a memory device. If a temperature of a particular memory block among the plurality of memory blocks meets or exceeds a threshold operational temperature corresponding to a memory device containing the plurality of memory blocks, the particular memory block can be allocated for receipt and/or storage of data.