Abstract: Apparatuses may include a device substrate including a microelectronic device and bond pads proximate to an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball positioned and configured to carry a high-bandwidth data signal or a high-frequency clock signal may be located laterally or longitudinally adjacent to no more than one other ball of the ball grid array configured to carry a high-bandwidth data signal or a high-frequency clock signal. Each ball positioned and configured to carry a high-bandwidth data signal may be located only diagonally adjacent to any other balls configured to carry a high-bandwidth data signal or a high-frequency clock signal.

Abstract: Methods, systems, and devices for virtualized authentication device are described. A virtual device (such as a virtual machine) may be permitted to access secured data within a memory device by an authentication process. The memory device may generate cryptographic keys in portions of the memory device and assign the cryptographic keys to the virtual machines. The virtual machine may use an authentication process using the cryptographic keys to access the secure data in the memory device. The authentication process may include authenticating the identity of the virtual machine and the code operating on the virtual machine based upon comparing cryptographic keys received from the virtual machines to the assigned cryptographic keys in the partitions of the memory device. Once both the identity of the virtual machine is authenticated, the virtual machine may be permitted to access the secure data in the memory device.

Abstract: Methods, systems, and devices for device reset alert mechanism are described. The memory system may identify a fault condition associated with resetting the memory system and set, in a register associated with event alerts of the memory system, a first indication for a reset of the memory system. In some cases, the memory system may transmit a message that includes a second indication that the register associated with event alerts of the memory system has been changed based on setting the register. The memory system may reset one or more components of the memory system based on the first indication and the second indication.

Abstract: A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, control logic circuitry including transistors at least partially overlying the first semiconductor structure, and a first isolation material covering the first semiconductor structure and the control logic circuitry. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material of the second microelectronic device structure is bonded to the first isolation material of the first microelectronic device structure to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure.

Abstract: Methods, systems, and devices for payload validation for a memory system are described. A payload receiver may be a device that includes an array of memory cells configured to store data, and a payload transmitter may be a host of a payload receiver (e.g., a host device) or another device that is in communication with the payload receiver. A payload receiver may be configured to receive an information payload and a signature associated with the information payload. The received signature may be based on the information payload and an identifier of the payload receiver previously provided to the payload transmitter. The payload receiver may generate a signature based on the information payload and the identifier of the payload receiver (e.g., as stored or cached at the payload receiver), and authenticate the information payload based on the received signature and the generated signature.

Abstract: A processing device in a memory sub-system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device further determines a syndrome for the sense word using the plurality of parity check equation results and determines whether the syndrome for the sense word satisfies a codeword criterion. Responsive to the syndrome for the sense word not satisfying the codeword criterion, the processing device performs an iterative low density parity check (LDPC) correction process using a scaled bit flip threshold to correct one or more errors in the sense word.

Abstract: An apparatus includes: a first semiconductor substrate; a plurality of first regions extending in parallel in a first direction on the first semiconductor substrate, each of the plurality of first regions including a plurality of first shallow trench isolations (STI) therein; and a plurality of second regions each extending between corresponding adjacent two of the plurality of first regions, each of the plurality of second regions including a plurality of second STIs and a plurality of active regions arranged alternately and in line in the first direction. Each of the plurality of second STIs has a greater depth than each of the plurality of first STIs.

Abstract: Described apparatuses and methods provide system error correction code (ECC) circuitry routing that segregates even sense amp (SA) line data sets and odd SA line data sets in a memory, such as a low-power dynamic random-access memory. A memory device may include one or more dies, and a die can have even SA line data sets and odd SA line data sets. The memory device may also include ECC circuitry comprising one or more ECC engines. By segregating the data sets, instead of coupling even and odd SA line data sets to a single ECC engine, double-bit errors on a single word line may be separated into two single-bit errors. Thus, by utilizing system ECC circuitry routing in this way, even a one-bit ECC algorithm may be used to correct double bits, which may increase data reliability.

Abstract: Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.

Abstract: Described apparatuses and methods relate to adaptive refresh staggering for a memory system that may support a nondeterministic protocol. To help manage power-delivery networks in a memory system, a memory device can include logic that can be programmed to stagger the start of refresh operations for each die upon receiving a command to enter a lower-power mode, such as self-refresh. The staggered start can be implemented at a channel level, a package level, or both. The programming sets a delay for each die so that initiation of refresh operations is staggered. Thus, a first die can initiate refresh operations when a command to enter the lower-power mode is received (e.g., approximately zero delay). However, initiation of refresh operations for subsequent dies (e.g., “after” the first die) is delayed, which can reduce peak current draw and power consumption.

Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

Abstract: An apparatus that includes first, second, third and fourth circuit regions arranged in a first direction in numerical order. The first circuit region includes a first global power supply line extending in a second direction vertical to the first direction and a first local power supply line, the first local power supply line being branched from the first global power supply line and extending in the first direction across the second, third and fourth regions. The third circuit region includes a first power switch coupled between the first local power supply line and an internal power supply line extending in the first direction across the first, second, third and fourth regions. Each of the second and fourth regions includes a circuit coupled to the first local power supply line and an additional circuit coupled to the internal power supply line.

Abstract: Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a flight of stairs. The stairs individually comprise a tread comprising conducting material of one of the conductive tiers. A conductive-via construction extends downwardly from and directly below the conducting material of individual of the treads to circuitry that is directly below the stack. The conductive-via construction comprises an insulator lining circumferentially about conductor material. The insulator lining and the conductor material extend downwardly from the individual treads through that portion of the stack that is directly thereunder.

Abstract: A method used in forming memory circuitry comprises forming transistors individually comprising one source/drain region and another source/drain region. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. Openings are formed through insulative material that is directly above the transistors and into the another source/drain regions. Individual of the openings are directly above individual of the another source/drain regions. A laterally-outer insulator material is formed in the individual openings within and below the insulative material. A laterally-inner insulator material is formed in the individual openings within and below the insulative material laterally-over the laterally-outer insulator material. The laterally-outer insulator material and the laterally-inner insulator material are directly against one another and have an interface there-between.

Abstract: Methods, systems, and devices for a dynamic row hammering threshold for memory are described. A memory device may implement a dynamic threshold, such as a threshold quantity of activate operations or a row hammering threshold, for a set of multiple rows of the memory device. For example, the memory device may determine a quantity of rows which exceed a row hammering threshold during a refresh duration and a total quantity of activate operations performed across the set of rows during the refresh duration, and may alter the dynamic threshold based on the quantity of rows, the quantity of activate operations, or both. By altering the dynamic threshold, the memory device may decrease a likelihood that a relatively large quantity of refresh operations for rows that are close to being hammered occur within a short time span.

Abstract: A computing system (100) having a storage system that includes a storage device (130) and a host device (105), where the host device (105) is configured to issue memory access commands to the storage device (130). The computing system (100) further includes a prediction system (190) comprising processing circuitry that is configured to perform operations that cause the prediction system (190) to identify one or more components of the storage system (918) that limit random rad performance of the storage system (918). The operations further cause the prediction system (190) to obtain characterization data that is indicative of the impact of the one or more components on random read performance and generate a model based on the characterization data to predict random read performance of the storage system (918).

Abstract: Methods, systems, and devices for secure self-purging memory partitions are described. Systems, techniques and devices are described herein in which data stored in a portion of a secure partition of memory may be removed from the secure partition. In some examples, a portion of secure partition may be allocated as self-purging memory such that data stored therein may be selectively removed in response to a logic address associated with the data being overwritten. In some cases, the data may be removed by programming the memory cells associated with the data to a specific voltage distribution. In some cases, the secure partition may include separate portions having different sets of operating parameters for access operations.

Abstract: Methods for manufacturing semiconductor devices having a flexible reinforcement structure, and associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a semiconductor device includes electrically coupling at least one semiconductor die to a redistribution structure on a first carrier. The semiconductor die can include a first surface facing the redistribution structure and a second surface spaced apart from the redistribution structure. The method also includes reducing a thickness of the semiconductor die to no more than 10 ?m. The method further includes coupling a flexible reinforcement structure to the second surface of the at least one semiconductor die.

Abstract: Methods, systems, and devices related to signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may also include a controller configured to determine whether data associated with an address of the memory array is stored in one or more cache blocks of the signal development cache. As an example, the memory device may determine whether the data is stored in one or more cache blocks of the signal development cache based on mapping information associated with the address of the memory array.

Abstract: An apparatus includes a processing resource configured to receive a feature vector of a data stream. The feature vector includes a set of feature values. The processing resource is further configured to calculate a set of feature labels based at least in part on the set of feature values to generate a label vector, provide the label vector to another processing resource, and receive a plurality of classifications corresponding to each feature label of the label vector from the other processing resource. The plurality of classifications are generated based at least in part on a respective range of feature values of the set of feature values. The processing resource is configured to then combine the plurality of classifications to generate a final classification of the data stream.