Patents Assigned to Nanya Technology Corporation
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Patent number: 11978785Abstract: A method of manufacturing a semiconductor structure is provided. The method includes providing a semiconductor substrate having an active region, forming a fin structure in the active region, and forming a conductive element on the body portion and the first tapered portion of the fin structure. The fin structure includes a body portion, and a first tapered portion protruding from an upper surface of the body portion.Type: GrantFiled: December 17, 2021Date of Patent: May 7, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Jhen-Yu Tsai
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Patent number: 11978662Abstract: A method for preparing a semiconductor device, includes: forming a first dielectric structure and a second dielectric structure over a semiconductor substrate; forming a conductive material over the first dielectric structure and the second dielectric structure, wherein the conductive material extends into a first opening between the first dielectric structure and the second dielectric structure; partially removing the conductive material to form a first bit line and a second bit line in the first opening; forming a first capacitor contact and a second capacitor contact in the first dielectric structure and the second dielectric structure, respectively; forming a sealing dielectric layer over the first bit line and the second bit line such that an air gap is formed between the sealing dielectric layer and the semiconductor substrate; and forming a first capacitor and a second capacitor over the first capacitor contact and the second capacitor contact, respectively.Type: GrantFiled: August 11, 2023Date of Patent: May 7, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Liang-Pin Chou
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Patent number: 11978500Abstract: The present disclosure provides a memory device. The memory device includes a substrate, a dielectric layer, a first metallization layer, a first channel layer, a second metallization layer, and a second channel layer. The dielectric layer is disposed on the substrate. The first metallization layer is disposed within the dielectric layer and extends along a first direction. The first channel layer is surrounded by the first metallization layer. The second metallization layer is disposed within the dielectric layer and extends along the first direction. The second channel layer is surrounded by the second metallization layer. The first metallization layer includes a first protruding portion protruding toward the second metallization layer.Type: GrantFiled: May 25, 2022Date of Patent: May 7, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Jar-Ming Ho
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Publication number: 20240145024Abstract: A test device method includes: setting a core voltage of a memory device to a first voltage value and a peripheral voltage of the memory device to a second voltage value; testing the memory device by accessing the memory device based on the core voltage and the at least one peripheral voltage; adjusting the core voltage to a third voltage value and the at least one peripheral voltage of the memory device to a fourth voltage value; testing the memory device by reading the memory device based on the core voltage and the at least one peripheral voltage; adjusting the core voltage to a fifth voltage value and the at least one peripheral voltage of the memory device to a sixth voltage value; and testing the memory device by reading the memory device based on the core voltage and the at least one peripheral voltage.Type: ApplicationFiled: October 31, 2022Publication date: May 2, 2024Applicant: NANYA TECHNOLOGY CORPORATIONInventor: Yao-Chang Chiu
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Patent number: 11966680Abstract: The disclosure provides a system to simulate a simulated noise on the power zone block of a substrate. The system comprises a signal trace and a signal generating circuit. The signal trace is disposed adjacent to the power zone block. The signal generating circuit is electrically coupled to the signal trace, configured to transmit an alternating current signal over the signal trace. The alternating current signal transmitted over the signal trace is configured to induce a simulated noise on the power zone block, and a waveform of the simulated noise is determined by a frequency of the alternating current signal.Type: GrantFiled: July 19, 2021Date of Patent: April 23, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Kuo-Chiang Hung, Tsung-Ho Li
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Patent number: 11967628Abstract: A semiconductor structure includes a substrate, an isolation layer, a dielectric layer, an insulation layer, a conductor and a capping layer. The substrate has a concave portion. The isolation layer is located on a top surface of the substrate. The dielectric layer is located on the isolation layer. The insulation layer is located on a surface of the concave portion and extends to a sidewall of the isolation layer. The conductor is located on the insulation layer in the concave portion. The conductor has a first top surface and a second top surface, and the first top surface is closer to the dielectric layer than the second top surface. The capping layer is located in the concave portion and covers the conductor.Type: GrantFiled: July 6, 2023Date of Patent: April 23, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Chih-Wei Huang, Hsu-Cheng Fan, En-Jui Li
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Patent number: 11967612Abstract: A method of manufacturing a semiconductor structure includes the following steps: providing a first semiconductor wafer, wherein the first semiconductor wafer includes a first dielectric layer and at least one first top metallization structure embedded in the first dielectric layer, and a top surface of the first dielectric layer is higher than a top surface of the first top metallization structure by a first distance; providing a second semiconductor wafer, wherein the second semiconductor wafer includes a second dielectric layer and at least one second top metallization structure embedded in the second dielectric layer, and a top surface of the second top metallization structure is higher than a top surface second dielectric layer of the by a second distance; and hybrid-bonding the first semiconductor wafer and the second semiconductor wafer.Type: GrantFiled: December 9, 2021Date of Patent: April 23, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Ting-Cih Kang, Hsih-Yang Chiu
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Patent number: 11959939Abstract: The present application discloses a chip socket, a testing fixture and a chip testing method thereof. The chip socket includes a pedestal, a plurality of conductive traces, a plurality of clamp structures, and a plurality of electrical contacts. The plurality of conductive traces are formed in the pedestal. The plurality of clamp structures are conductive and disposed on the first surface of the pedestal, and at least one of the plurality of clamp structures is coupled to a corresponding conductive trace and configured to clamp a solder ball of a chip to be tested. The plurality of electrical contacts are disposed on the second surface of the pedestal, and at least one of the plurality of electrical contacts is coupled to a corresponding clamp structure through a corresponding conductive trace.Type: GrantFiled: September 7, 2021Date of Patent: April 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Shih-Ting Lin
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Patent number: 11963345Abstract: The present disclosure provides a semiconductor structure having a fin structure. The semiconductor includes a substrate defined with an active region. A first gate structure is disposed in the active region and includes a dielectric material. A second gate structure is disposed in the active region and includes the dielectric material. A fin structure having a first top surface is arranged to alternate with the first gate structure and the second gate structure. The first gate structure has a second top surface and the second gate structure has a third top surface. The second top surface and the third top surface are lower than the first top surface.Type: GrantFiled: March 24, 2023Date of Patent: April 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Min-Chung Cheng
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Patent number: 11961578Abstract: A memory device includes a data array, a parity array and an ECC circuit. The ECC circuit is coupled to the data array and the parity array. In a first test mode, the ECC function of the ECC circuit is disabled, and in a second test mode, the ECC circuit directly accesses the parity array to read or write parity information through the parity array.Type: GrantFiled: September 1, 2022Date of Patent: April 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Jyun-Da Chen
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Publication number: 20240118964Abstract: A fault analysis device and a fault analysis method of the fault analysis device are provided. A sensing circuit senses a first distorted signal on a first signal transmission path of an abnormal signal device when the abnormal signal device performs a preset operation. A signal generating circuit provides a fault test signal to a second signal transmission path of a standard device corresponding to the first signal transmission path when the standard device performs the preset operation, so as to generate a second distorted signal on the second signal transmission path, where the first distorted signal and the second distorted signal have the same signal distortion characteristics.Type: ApplicationFiled: October 5, 2022Publication date: April 11, 2024Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Chien Yu Chen, Meng-Kai Hsieh
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Patent number: 11955196Abstract: A voltage generating device includes a clock signal generator, a voltage regulator and a pump circuit. The clock signal generator generates a clock signal according to an enable signal. The voltage regulator generates and adjusts a first voltage according to a reference voltage and the enable signal. The pump circuit receives the clock signal, the first voltage and a second voltage, wherein the pump circuit performs a voltage pump operation to generate an output voltage based on the clock signal according to the first voltage and the second voltage. The output voltage equals to a summation of the first voltage and the second voltage.Type: GrantFiled: July 13, 2022Date of Patent: April 9, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Ting-Shuo Hsu, Chih-Jen Chen
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Patent number: 11955989Abstract: A memory device includes a data array, a parity array and an ECC circuit. The ECC circuit is coupled to the data array and the parity array. In a first test mode, the ECC function of the ECC circuit is disabled, and in a second test mode, the ECC circuit directly accesses the parity array to read or write parity information through the parity array.Type: GrantFiled: August 21, 2022Date of Patent: April 9, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Chih-Yuan Wen
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Patent number: 11955564Abstract: The present application discloses a method for fabricating a semiconductor device with an oxidized intervention layer. The method includes providing a substrate; forming a tunneling insulating layer over the substrate; forming a floating gate over the tunnel oxide layer; forming a dielectric layer over the floating gate; forming a control gate over the dielectric layer; and performing a lateral oxidation process over the substrate, wherein a process temperature of the lateral oxidation process is between about 300° C. and about 600° C.Type: GrantFiled: January 24, 2022Date of Patent: April 9, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Te-Yin Chen
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Patent number: 11955474Abstract: An electrostatic discharge (ESD) protection circuit is provided. The protection circuit includes a MOS transistor and a resistor. The MOS transistor is electrically coupled to a core circuit. The resistor is electrically coupling to a gate of the MOS transistor for creating a bias on the gate to directing an ESD current to a ground when an ESD event occurs on the core circuit. A layout of the MOS transistor is spaced apart from a layout of the core circuit by a layout of a dummy structure. The resistor is formed by utilizing a portion of the dummy structure.Type: GrantFiled: August 22, 2022Date of Patent: April 9, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Fang-Wen Liu
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Patent number: 11955427Abstract: An electrical fuse matrix includes a plurality of anti-fuse structures, a plurality of top metal plates, and a plurality of bottom metal plates. The anti-fuse structures are arranged in a matrix, and each of the anti-fuse structure includes a top conductive structure, a bottom conductive structure, and a dielectric film disposed between the top conductive structure and the bottom conductive structure. The anti-fuse structure has an hourglass shape. The top metal plates are disposed on the top conductive structures. The bottom metal plates are disposed on the bottom conductive structures.Type: GrantFiled: December 8, 2021Date of Patent: April 9, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Hsih-Yang Chiu
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Patent number: 11955446Abstract: The present disclosure relates to a method for forming a semiconductor device structure. The method includes forming a first semiconductor die and forming a second semiconductor die. The first semiconductor die includes a first metal layer, a first conductive via over the first metal layer, and a first conductive polymer liner surrounding the first conductive via. The second semiconductor die includes a second metal layer, a second conductive via over the second metal layer, and a second conductive polymer liner surrounding the second conductive via. The method also includes forming a conductive structure electrically connecting the first metal layer and the second metal layer by bonding the second semiconductor die to the first semiconductor die. The conductive structure is formed by the first conductive via, the first conductive polymer liner, the second conductive via, and the second conductive polymer liner.Type: GrantFiled: November 23, 2022Date of Patent: April 9, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Yu-Han Hsueh
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Publication number: 20240110980Abstract: A test interface circuit includes N switches and N resistors, wherein N is a positive integer. A first end of each of the N switches is coupled to each of N test connection ends, a second end of each of the N switches receives a reference voltage. Each of the N first resistors is coupled to each of the N switches in series between each of the N test connection ends and the reference voltage. Wherein, each of the N switches is controlled by each of N control signals to be turned on or cut off.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Che-Wei Chen, Kai-Li Liu, YuLin Sung
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Patent number: 11948968Abstract: The present disclosure provides a method for preparing a semiconductor device structure. The method includes forming a capacitor contact over a semiconductor substrate, and forming a base layer over the capacitor contact. The method also includes forming a dielectric layer over the base layer, and performing a first doping process to form a first doped region in the dielectric layer. The method further includes etching the dielectric layer such that a sidewall of the dielectric layer is aligned with a sidewall of the first doped region, and removing the first doped region to form a first gap structure in the dielectric layer after the dielectric layer is etched. In addition, the method includes forming a surrounding portion along sidewalls of the dielectric layer and a first interconnect portion in the first gap structure by a deposition process.Type: GrantFiled: February 13, 2023Date of Patent: April 2, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Hung-Chi Tsai
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Patent number: 11948991Abstract: The present disclosure provides semiconductor structure having an electrical contact. The semiconductor structure includes a semiconductor substrate and a doped polysilicon contact. The doped polysilicon contact is disposed over the semiconductor substrate. The doped polysilicon contact includes a dopant material having a dopant concentration equaling or exceeding about 1015 atom/cm3.Type: GrantFiled: December 9, 2021Date of Patent: April 2, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Chen-Hao Lien, Cheng-Yan Ji, Chu-Hsiang Hsu