Abstract: The present disclosure relates to a method for forming a semiconductor device structure. The method includes forming a first semiconductor die and forming a second semiconductor die. The first semiconductor die includes a first metal layer, a first conductive via over the first metal layer, and a first conductive polymer liner surrounding the first conductive via. The second semiconductor die includes a second metal layer, a second conductive via over the second metal layer, and a second conductive polymer liner surrounding the second conductive via. The method also includes forming a conductive structure electrically connecting the first metal layer and the second metal layer by bonding the second semiconductor die to the first semiconductor die. The conductive structure is formed by the first conductive via, the first conductive polymer liner, the second conductive via, and the second conductive polymer liner.

Abstract: An electrical fuse matrix includes a plurality of anti-fuse structures, a plurality of top metal plates, and a plurality of bottom metal plates. The anti-fuse structures are arranged in a matrix, and each of the anti-fuse structure includes a top conductive structure, a bottom conductive structure, and a dielectric film disposed between the top conductive structure and the bottom conductive structure. The anti-fuse structure has an hourglass shape. The top metal plates are disposed on the top conductive structures. The bottom metal plates are disposed on the bottom conductive structures.

Abstract: A test interface circuit includes N switches and N resistors, wherein N is a positive integer. A first end of each of the N switches is coupled to each of N test connection ends, a second end of each of the N switches receives a reference voltage. Each of the N first resistors is coupled to each of the N switches in series between each of the N test connection ends and the reference voltage. Wherein, each of the N switches is controlled by each of N control signals to be turned on or cut off.

Abstract: The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate, forming a first pad above the substrate, forming a first redistribution conductive layer on the first pad, and forming a first redistribution thermal release layer on the first redistribution conductive layer. The first redistribution conductive layer and the first redistribution thermal release layer together form a first redistribution structure and the first redistribution thermal release layer is configured to sustain a thermal resistance between about 0.04° C. cm2/Watt and about 0.25° C. cm2/Watt.

Abstract: The present disclosure provides a method for preparing a semiconductor device structure. The method includes forming a capacitor contact over a semiconductor substrate, and forming a base layer over the capacitor contact. The method also includes forming a dielectric layer over the base layer, and performing a first doping process to form a first doped region in the dielectric layer. The method further includes etching the dielectric layer such that a sidewall of the dielectric layer is aligned with a sidewall of the first doped region, and removing the first doped region to form a first gap structure in the dielectric layer after the dielectric layer is etched. In addition, the method includes forming a surrounding portion along sidewalls of the dielectric layer and a first interconnect portion in the first gap structure by a deposition process.

Abstract: The present disclosure provides semiconductor structure having an electrical contact. The semiconductor structure includes a semiconductor substrate and a doped polysilicon contact. The doped polysilicon contact is disposed over the semiconductor substrate. The doped polysilicon contact includes a dopant material having a dopant concentration equaling or exceeding about 1015 atom/cm3.

Abstract: A method of manufacturing a semiconductor structure is provided. A conductive layer is formed on a precursor memory structure. A target layer is formed on the conductive layer. A first photoresist with a first opening is formed on the target layer. A spacer is formed on sidewalls of the first opening. A second photoresist with a second opening is formed on the target layer and the spacer. The target layer is patterned by the second photoresist and the spacer to form a first patterned target layer. A third photoresist with a third opening is formed on the first patterned target layer. The first patterned target layer is patterned by the third photoresist to form a second patterned target layer. The conductive layer is patterned by the second patterned target layer to form a patterned conductive layer including a ring structure aligned with a source/drain region.

Abstract: A semiconductor device and a circuit are provided. The semiconductor device includes a substrate, a first gate structure, a first doped region, and a capacitor structure. The substrate includes a first well region having a first conductive type. The first gate structure is disposed on the substrate. The first doped region is in the substrate and has a second conductive type different from the first conductive type. The first gate structure and the first doped region are included in a first transistor. The capacitor structure includes a first electrode electrically coupled to the first doped region. The second doped region is in the substrate and has the second conductive type. The second doped region is electrically coupled to the first electrode of the capacitor structure and the first doped region.

Abstract: A semiconductor circuit and a semiconductor device for determining a status of a fuse element are provided. The semiconductor circuit includes a configurable reference resistor unit with a first terminal receiving a first power signal and a second terminal electrically coupled to the fuse element. The semiconductor circuit also includes a first switching circuit electrically connecting the configurable reference resistor unit and the fuse element and a latch circuit for reading an evaluation signal of a first node between the configurable reference resistor unit and the fuse element.

Abstract: A manufacturing method of a semiconductor device includes forming a contact opening in a wafer. The wafer includes a substrate, a gate structure over the substrate and a dielectric layer over the substrate and surrounding the gate structure, and the contact opening passes through the dielectric layer and exposes the substrate. A recess is formed in the substrate such that the recess is connected to the contact opening. An oxidation process is performed to convert a portion of the substrate exposed in the recess to form a protection layer lining a sidewall and a bottom surface of the recess. The protection layer is etched back to remove a first portion of the protection layer in contact with the bottom surface of the recess of the substrate. A metal alloy structure is formed at the bottom surface of the recess of the substrate.

Abstract: A probe station includes a frame, a platform, a testing equipment, a probe holder and at least one probe. The frame defines an accommodation space. The platform is connected with the frame. The platform has an opening. The opening is communicated with the accommodation space. The testing equipment is at least partially disposed in the accommodation space and is at least partially exposed through the opening. The probe holder is disposed on the platform. The probe is held by the probe holder. The probe holder is configured to control the probe to contact with a device under test disposed on the testing equipment through the opening.

Abstract: A method for preparing a semiconductor device structure is provided. The method includes forming a target layer over a semiconductor substrate; forming an energy-sensitive layer over the target layer; performing a first energy treating process to form a plurality of first treated portions in the energy-sensitive layer; performing a second energy treating process to form a plurality of second treated portions in the energy-sensitive layer; removing the first treated portions and the second treated portions to respectively form a plurality of first openings and a plurality of second openings; transferring the first openings and the second openings into the target layer to respectively form a plurality of third openings and a plurality of fourth openings; and transferring the third openings and the fourth openings into the semiconductor substrate to respectively form a plurality of fifth openings and a plurality of sixth openings.

Abstract: The present application discloses a semiconductor device including a substrate; a first semiconductor stack having a first threshold voltage and comprising a first insulating stack positioned on the substrate; a second semiconductor stack having a second threshold voltage and comprising a second insulating stack positioned on the substrate; and wherein the first threshold voltage is different the second threshold voltage; a thickness of the first insulating stack is different from a thickness of the second insulating stack.

Abstract: A method of manufacturing a semiconductor structure includes: forming a first oxide layer over a landing pad layer; forming a middle patterned dielectric layer over the first oxide layer; sequentially forming a second oxide layer and a top dielectric layer over the middle patterned dielectric layer; forming a trench through the top dielectric layer, the second oxide layer and the first oxide layer; conformally forming a bottom conductive layer in the trench; removing a portion of the top dielectric layer adjacent to the trench to expose a portion of the second oxide layer beneath the portion of the top dielectric layer; and performing an etching process to remove the second oxide layer and the first oxide layer. A semiconductor structure is also provided.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a contact structure, a first conductive element, and a first dielectric spacer structure. The semiconductor substrate includes an active region and an isolation structure. The contact structure is on the active region of the semiconductor substrate. The first conductive element is on the isolation structure of the semiconductor substrate. The first dielectric spacer structure is between the contact structure and the first to conductive element. The first dielectric spacer structure has a first concave surface facing the first conductive element.

Abstract: A manufacturing method of a semiconductor device includes forming an opening in a substrate, implanting a dopant in the substrate from a sidewall of the opening such that a doping region is formed in the substrate at the sidewall of the opening, filling a dielectric material in the opening to form a first dielectric structure after implanting the dopant in the substrate from the sidewall of the opening, and forming a passing word line in the dielectric structure.

Abstract: A method of manufacturing a memory structure is provided. The method includes forming a first gate structure, a second gate structure, and a plurality of source/drain regions in a substrate, in which the plurality of source/drain regions are disposed on opposite sides of the first gate structure and the second gate structures; performing a dry etching process to form a trench between the first gate structure and the second gate structure; performing a wet etching process to expand the trench, in which the expanded trench has a hexagonal shaped cross section profile; and forming a bit line contact in the expanded trench.

Abstract: The present disclosure provides a semiconductor structure including a substrate; a redistribution layer (RDL) disposed over the substrate, and including a dielectric layer over the substrate, a conductive plug extending within the dielectric layer, and a bonding pad adjacent to the conductive plug and surrounded by the dielectric layer; and a conductive bump disposed over the conductive plug, wherein the bonding pad is at least partially in contact with the conductive plug and the conductive bump. Further, a method of manufacturing the semiconductor structure is also provided.

Abstract: The present disclosure relates to a semiconductor device with a contact structure and a method for preparing the semiconductor device. The semiconductor device includes a source/drain structure disposed over a semiconductor substrate, and a dielectric layer disposed over the source/drain structure. The semiconductor device also includes a polysilicon stack disposed over the source/drain structure and surrounded by the dielectric layer. The polysilicon stack includes a first polysilicon layer and a second polysilicon layer disposed over the first polysilicon layer. The first polysilicon layer is undoped, and the second polysilicon layer is doped. The semiconductor device further includes a contact structure disposed directly over the polysilicon stack and surrounded by the dielectric layer.

Abstract: An electrostatic discharge (ESD) protection circuit is provided. The protection circuit includes a MOS transistor and a resistor. The MOS transistor is electrically coupled to a core circuit. The resistor is electrically coupling to a gate of the MOS transistor for creating a bias on the gate to directing an ESD current to a ground when an ESD event occurs on the core circuit. A layout of the MOS transistor is spaced apart from a layout of the core circuit by a layout of a dummy structure. The resistor is formed by utilizing a portion of the dummy structure.