Abstract: A manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.

Abstract: The present application provides a memory device having a word line with an improved adhesion between a work function member and a conductive layer. The memory device includes a semiconductor substrate defined with an active area and including a recess extending into the semiconductor substrate, and a word line disposed within the recess, wherein the word line includes a first insulating layer disposed within and conformal to the recess, a conductive layer surrounded by the first insulating layer, a conductive member enclosed by the conductive layer, and a second insulating layer disposed over the conductive layer and conformal to the first insulating layer. A method of manufacturing the memory device is also disclosed.

Abstract: The present disclosure provides a semiconductor device, a semiconductor assembly and method of manufacturing the semiconductor assembly. The semiconductor device includes a substrate, a conductive feature in the substrate, an isolation liner between the substrate and the conductive feature, and a main component in the substrate. The conductive feature includes first to third blocks. The first block has a uniform first critical dimension, wherein the main component is disposed around the first block. The second block has a uniform second critical dimension greater than the first critical dimension. The third block is interposed between the first block and the second block and has varying third critical dimensions.

Abstract: The present application discloses a method for fabricating a semiconductor device. The method includes providing a first semiconductor structure; and forming a first connecting structure comprising a first connecting insulating layer on the first semiconductor structure, a plurality of first connecting contacts in the first connecting insulating layer, and a plurality of first supporting contacts in the first connecting insulating layer.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes forming a first patterned layer over a substrate; forming a second patterned layer over the substrate and alternately arranged with the first patterned layer; performing an etching, thereby forming an arched surface of the first patterned layer and an arched surface of the second patterned layer; forming a sacrificial layer over the first patterned layer and the second patterned layer, wherein a plurality of air gaps are defined by the substrate, the first patterned layer, the second patterned layer and the sacrificial layer; removing the sacrificial layer above the plurality of air gaps, thereby forming a planar top surface of the first patterned layer and a planar top surface of the second patterned layer; and patterning the substrate using the first patterned layer and the second patterned layer as a mask.

Abstract: The present application discloses a method for preparing a semiconductor device including an electronic fuse control circuit. The method includes providing a chip including an electronic fuse control circuit, wherein the electronic fuse control circuit includes a program voltage pad, a fuse element, a latch, a plurality of resistor selection pads, and a plurality of bonding option units. The method further includes providing a substrate including a first voltage bonding pad and a plurality of second voltage bonding pads, disposing the chip on the substrate, bonding the first voltage bonding pad to the program voltage pad, and bonding at least one of the plurality of second voltage bonding pads to at least one of the plurality of resistor selection pads.

Abstract: The present application discloses a method for fabricating a semiconductor device with slanted conductive layers. The method for fabricating a semiconductor device includes providing a substrate, forming a first insulating layer above the substrate, forming first slanted recesses along the first insulating layer, and forming first slanted conductive layers in the first slanted recesses and a top conductive layer covering the first slanted conductive layers.

Abstract: A method for forming a semiconductor device includes forming a conductive contact over a semiconductor substrate, and forming a first dielectric layer covering the conductive contact. The method also includes partially removing the first dielectric layer to form an opening exposing a top surface of the conductive contact, and forming a bottom electrode covering sidewalls of the opening and the top surface of the conductive contact. The method further includes depositing a second dielectric layer over the bottom electrode using a first process, and depositing dielectric portions over the second dielectric layer and at top corners of the opening using a second process. The first process has a first step coverage, the second process has a second step coverage, and the second step coverage is smaller than the first step coverage. The method includes forming a top electrode covering the second dielectric layer and the dielectric portions.

Abstract: A memory control circuit and a refresh method for a dynamic random access memory (DRAM) array are provided. The memory control circuit includes a mode register circuit, a command decoder and a refresh circuit. The mode register circuit includes a plurality of mode registers. The command decoder receives a refresh command and sets a flag of a target mode register corresponding to the refresh command among the plurality of mode registers to a setting value. The refresh circuit refreshes the DRAM array in response to the refresh command through the command decoder and the setting value of the flag of the target mode register.

Abstract: A memory device includes a data array, a parity array and an ECC circuit. The ECC circuit is coupled to the data array and the parity array. In a first test mode, the ECC function of the ECC circuit is disabled, and in a second test mode, the ECC circuit directly accesses the parity array to read or write parity information through the parity array.

Abstract: A voltage generator and a voltage generating method are provided. The voltage generator includes at least one first charge pump circuit, at least one second charge pump circuit, an oscillator, a passing circuit, and a voltage detector. The first charge pump circuit is configured to receive a clock signal to generate a first pump voltage. The second charge pump circuit is configured to receive the clock signal to generate a first pump voltage. The oscillator is configured to provide the clock signal. The passing circuit is configured to receive the clock signal, a power-on detection signal and an external command. The voltage detector is configured to receive an operation voltage, and generate the power-on detection signal by detecting the operation voltage. The passing circuit determines whether to transmit the clock signal to the second charge pump circuit or not to activate or deactivate the second charge pump circuit.

Abstract: The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate, forming a first conductive layer above the substrate, concurrently forming a bottom conductive layer and a redistribution structure above the first conductive layer, forming a programmable insulating layer on the bottom conductive layer, and forming a top conductive layer on the programmable insulating layer. The bottom conductive layer, the programmable insulating layer, and the top conductive layer together configure a programmable unit. The bottom conductive layer and the redistribution structure are electrically coupled to the first conductive layer.

Abstract: The present disclosure provides a dynamic random access memory (DRAM) array. The memory array includes a semiconductor substrate, an isolation structure and contact enhancement sidewall spacers. The semiconductor substrate has a trench defining laterally separate active areas formed of surface regions of the semiconductor substrate. Top surfaces of a first group of the active areas are recessed with respect to top surfaces of a second group of the active areas. The isolation structure is filled in the trench and in lateral contact with bottom portions of the active areas. The contact enhancement sidewall spacers laterally surround top portions of the active areas, respectively.

Abstract: A fuse component, a semiconductor device, and a method of manufacturing a fuse component are provided. The fuse component includes an active region having a surface, a fuse dielectric layer extending from the surface of the active region into the active region, and a gate metal layer surrounded by the fuse dielectric layer.

Abstract: A memory device includes a data array, a parity array and an ECC circuit. The ECC circuit is coupled to the data array and the parity array. In a first test mode, the ECC function of the ECC circuit is disabled, and in a second test mode, the ECC circuit directly accesses the parity array to read or write parity information through the parity array.

Abstract: The present application discloses a method for fabricating a semiconductor device with graphene layers The method includes providing a substrate; forming a first passivation layer above the substrate; forming a redistribution layer on the first passivation layer; forming a first adjustment layer on the redistribution layer; forming a pad layer on the first adjustment layer; forming a second adjustment layer between the pad layer and the first adjustment layer; forming a second passivation layer on the first passivation layer; wherein the first adjustment layer and the second adjustment layer are formed of graphene.

Abstract: The fuse device includes a plurality of fuse circuits, a global latch circuit and a plurality of local latch circuits. The global latch circuit is coupled to the fuse circuits. The global latch circuit is used to sense the blown states of the fuse circuits at different times, so as to output the fuse information of the fuse circuits at the different times. The local latch circuits are coupled to the global latch circuits. Each of these local latch circuits latches the fuse information output by the global latch circuit at the different times.

Abstract: A method of measuring a fuse resistance includes steps as follows. A predetermined voltage value of a force voltage on a common ground (CGND) bus electrically connected to at least one fuse element, a first current value of a measured current through the CGND bus in a first condition, and a second current value of another measured current through the CGND bus in a second condition are preloaded. The second current value is subtracted from the first current value, so as to get a subtracted current value, thereby removing a value of a leakage current through the CGND bus. The predetermined voltage value is divided by the subtracted current value to equal the fuse resistance of the at least one fuse element.

Abstract: A method for fabricating a crown capacitor includes: forming a first supporting layer over a substrate; forming a second supporting layer above the first supporting layer; alternately stacking first and second sacrificial layers between the first and second supporting layers to collectively form a stacking structure; forming a recess extending through the stacking structure; performing an etching process to the first sacrificial layers at a first etching rate and the second sacrificial layers at a second etching rate greater than the first etching rate, such that each second sacrificial layer and immediately-adjacent two of the first sacrificial layers collectively define a concave portion; forming a first electrode layer over a surface of the recess in which the first electrode layer has a wavy structure; removing the first and second sacrificial layers; and forming a dielectric layer and a second electrode layer over the first electrode layer.

Abstract: A memory device includes a first chip, a second chip and a processor. The second chip is coupled to the first chip at a first node. The second chip includes a first capacitor and a first variable resistor. The first capacitor is coupled to the first node. The first variable resistor is coupled in series with the first capacitor. The processor is coupled to the first node, and is configured to perform a first read operation to the first chip via the first node. A method for operating a memory device is also disclosed herein.