Abstract: A voltage regulator for providing a word line voltage is provided. The voltage regulator includes a voltage divider, a comparator, a boost circuit and a bypass transistor. The voltage divider is coupled between the word line voltage and a low reference voltage. The voltage divider includes resistive elements connected in series at intermediate nodes. The comparator provides an enable signal according to a divided voltage value on a divided intermediate node among the intermediate nodes. The boost circuit boosts the word line voltage in response to the enable signal. A source terminal of the bypass transistor is connected to a first intermediate node among the intermediate nodes. A drain terminal of the bypass transistor is connected to a second intermediate node among the intermediate nodes. The bypass transistor is turned-off in response to the control signal having an intermediate voltage value on the first intermediate node.

Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a plurality of first mask patterns over the target layer. The method also includes forming a lining layer conformally covering the first mask patterns and the target layer. A first opening is formed over the lining layer and between the first mask patterns. The method further includes filling the first opening with a second mask pattern, and performing an etching process on the lining layer and the target layer using the first mask patterns and the second mask pattern as a mask such that a plurality of second openings are formed in the target layer.

Abstract: An off-chip driver (OCD), including a pull-up driver and a pull-down driver, is provided. The pull-up driver and the pull-down driver are coupled to an output pad. One of the pull-up driver and the pull-down driver includes a main driving circuit, an auxiliary driving circuit, a connection circuit, and a common impedance. The main driving circuit is used to perform an output driving operation on the output pad, and the auxiliary driving circuit is used to selectively perform the output driving operation on the output pad. A first terminal of the common impedance is coupled to a driving terminal of the main driving circuit and a driving terminal of the auxiliary driving circuit through the connection circuit. A second terminal of the common impedance is coupled to the output pad.

Abstract: A semiconductor device can be applied to a memory device. The semiconductor device of the disclosure includes a voltage sensor, a convertor and a command/address on-die-termination (CA_ODT) circuit. The voltage sensor receives a voltage setting command, and sense a voltage level of the voltage setting command to generate a sensing signal. The convertor generates a setting signal in response to the sensing signal. The CA_ODT circuit generates a power voltage for the memory device in response to the setting signal, wherein a voltage level of the power voltage corresponds to the voltage level of the voltage setting command.

Abstract: The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface is formed between the first device wafer and the second device wafer, wherein the second device wafer is electrically coupled to the first device wafer, and a function of the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.

Abstract: A manufacturing method of a semiconductor package is provided as follows. A semiconductor die is provided, wherein the semiconductor die comprises a semiconductor substrate, an interconnection layer and a through semiconductor via, the interconnection layer is disposed on an active surface of the semiconductor substrate, the through semiconductor via penetrates the semiconductor substrate from a back surface of the semiconductor substrate to the active surface of the semiconductor substrate. An encapsulant is provided to laterally encapsulate the semiconductor die. A through encapsulant via penetrating through the encapsulant is formed.

Abstract: The present application discloses a method for fabricating a semiconductor device including providing a first stacking structure comprising a first controller die, and a plurality of first storage dies sequentially stacked on the first controller die; providing a second stacking structure comprising a second controller die, and a plurality of second storage dies sequentially stacked on the second controller die; bonding the first controller die onto a bottom die through a plurality of first interconnect units; and bonding the second controller die onto the bottom die through a plurality of second interconnect units. The plurality of first storage dies respectively comprise a plurality of first storage units configured as a floating array. The plurality of second storage dies comprise a plurality of second storage units respectively comprising an insulator-conductor-insulator structure.

Abstract: The present application provides a memory device having word lines with improved resistance, and a manufacturing method of the memory device. The memory device includes a semiconductor substrate defined with a peripheral region and an array region at least partially surrounded by the peripheral region, and including a first recess extending into the semiconductor substrate and disposed in the array region; an isolation structure surrounded by the semiconductor substrate and disposed in the peripheral region; and a word line disposed within the first recess, wherein the word line includes an insulating layer conformal to the first recess and a conductive member surrounded by the insulating layer, and the conductive member includes a second recess extending into the conductive member and toward the semiconductor substrate. A method of manufacturing the memory device is also disclosed.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a semiconductor substrate including an active region and an isolation structure. The method also includes forming a contact structure on the active region of the semiconductor substrate. The method further includes forming a dielectric spacer on opposite sides of the contact structure. The method also includes forming a conductive element on the isolation structure of the semiconductor substrate, wherein the dielectric spacer has a concave surface facing the conductive element.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes providing a semiconductor substrate having a trench. The method also includes forming a first buffer layer in the trench. The method further includes forming a doped-polysilicon layer on the first buffer layer in the trench. The method also includes performing a thermal treatment on the doped-polysilicon layer.

Abstract: A semiconductor device and method for manufacturing the same are provided. The method includes providing a substrate including a plurality of active areas separated from each other. In some embodiments, the method also includes forming first mask structures on the substrate. In some embodiments, the method further includes forming a first protective layer covering the first mask structures and the substrate. In some embodiments, the first protective layer defines an area exposing a portion of the first mask structures and the substrate, and the area defined by the first protective layer has a zigzag edge in a top view. In addition, the method includes performing a first etching process to remove a portion of the substrate exposed from the first mask structures and the first protective layer to form trenches.

Abstract: A method for manufacturing a semiconductor device structure includes forming a first metallization line and a second metallization line extending along a first direction; forming a first isolation feature and a second isolation feature between the first metallization line and the second metallization line, wherein the first metallization line, the second metallization line, the first isolation feature and the second isolation feature define an aperture; forming a profile modifier within the aperture, wherein the profile modifier comprises a plurality of segments spaced apart from each other, wherein each of the segments are located at corners of the aperture; and forming a contact feature surrounded by the plurality of segments.

Abstract: A method for preparing a semiconductor device structure includes forming a first fin structure and a second fin structure over a semiconductor substrate, forming an isolation structure over the semiconductor substrate, partially removing the first fin structure and the second fin structure to form a recessed portion of the first fin structure and a recessed portion of the second fin structure, epitaxially growing a first source/drain (S/D) structure over the recessed portion of the first fin structure and a second S/D structure over the recessed portion of the second fin structure, partially removing the isolation structure through the first opening to form a second opening, and forming a contact etch stop layer (CESL) over the first S/D structure and the second S/D structure such that an air gap is formed and sealed in the first opening and the second opening.

Abstract: An electronic device and a method of controlling an electronic device are provided. The electronic device includes a first transistor having a first resistor, second resistor, first transistor, and second transistor. The second resistor is connected to the first resistor. The first transistor is connected to the first resistor in parallel and has a first bulk. The second transistor is connected to the second resistor in parallel and has a second bulk. The first bulk of the first transistor receives a first voltage and the first bulk of the second transistor receives a second voltage. The first voltage and the second voltage are different.

Abstract: The present disclosure provides a mothed of method of manufacturing a semiconductor device. The method includes steps of forming a dielectric layer on a substrate; etching the dielectric layer to create a plurality of openings in the dielectric layer; applying a sacrificial layer in at least one of the openings to cover at least a portion of the dielectric layer; forming at least one first conductive feature in the openings where the sacrificial layer is disposed and a plurality of bases in the openings where the sacrificial layer is not disposed; removing the sacrificial layer to form at least one air gap in the dielectric layer; and forming a plurality of protrusions on the bases.

Abstract: The present application discloses provides a method for fabricating a semiconductor device. The method includes providing a substrate, forming a sacrificial structure above the substrate, forming a supporting liner covering the sacrificial structure, forming an energy-removable layer covering the supporting liner, performing a planarization process until a top surface of the sacrificial structure is exposed, performing an etch process to remove the sacrificial structure and concurrently form a first opening in the energy-removable layer, forming covering liners on sidewalls of the first opening and on a top surface of the energy-removable layer, forming a first conductive feature in the first opening, and applying an energy source to turn the energy-removable layer into a porous insulating layer.

Abstract: The present disclosure provides a method for manufacturing a semiconductor device having a buried wordline. The method includes forming a first recessed portion in a first dielectric layer in a substrate; forming a second recessed portion spaced apart from the first recessed portion and in the substrate; disposing a protection layer on the substrate to cover the second recessed portion; and disposing a second dielectric layer on the first dielectric layer.

Abstract: The present disclosure relates to a semiconductor device with an air gap below a landing pad and a method for forming the semiconductor device. The semiconductor device includes a first lower plug and a second lower plug disposed over a semiconductor substrate. The semiconductor device also includes a first landing pad disposed over a top surface and upper sidewalls of the first lower plug, and a first upper plug disposed over the first landing pad and electrically connected to the first lower plug. A width of the first lower plug is greater than a width of the first upper plug. The semiconductor device further includes a dielectric layer disposed over the semiconductor substrate. The first lower plug, the second lower plug, the first landing pad and the first upper plug are disposed in the dielectric layer, and the dielectric layer includes an air gap disposed between the first lower plug and the second lower plug.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: providing a substrate; forming a bit line structure over the substrate; forming a spacer surrounding the bit line structure; forming a polysilicon layer covering the bit line structure and the spacer; performing a first etching operation on the polysilicon layer to obtain a first height of the polysilicon layer, wherein the first height is less than a height of the bit line structure or a height of the spacer; performing a second etching operation on a first portion of the spacer; and performing a third etching operation on the polysilicon layer to obtain a second height of the polysilicon layer, wherein the second height is less than the first height.

Abstract: A method of operating a testing system comprising a plurality of testing slots. The method comprising: testing the testing slots; obtaining a current testing data from the testing slots; determining whether one of the testing slots is abnormal by comparing the current testing data with a former testing data; shutting down the one of the testing slots and sending a repairing notification if the one of the testing slots is determined to be abnormal; performing a confirmation procedure to determine whether the one of the testing slots is repaired to be normal; and restarting the one of the testing slots if the one of the testing slots passes the confirmation procedure.