Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: providing a substrate; forming a bit line structure over the substrate; forming a spacer surrounding the bit line structure; forming a polysilicon layer covering the bit line structure and the spacer; performing a first etching operation on the polysilicon layer to obtain a first height of the polysilicon layer, wherein the first height is less than a height of the bit line structure or a height of the spacer; performing a second etching operation on a first portion of the spacer; and performing a third etching operation on the polysilicon layer to obtain a second height of the polysilicon layer, wherein the second height is less than the first height.

Abstract: A method of operating a testing system comprising a plurality of testing slots. The method comprising: testing the testing slots; obtaining a current testing data from the testing slots; determining whether one of the testing slots is abnormal by comparing the current testing data with a former testing data; shutting down the one of the testing slots and sending a repairing notification if the one of the testing slots is determined to be abnormal; performing a confirmation procedure to determine whether the one of the testing slots is repaired to be normal; and restarting the one of the testing slots if the one of the testing slots passes the confirmation procedure.

Abstract: An electrical over stress protection device is provided. A detection circuit detects an input voltage from a pad, provides a first discharge path when the input voltage is higher than a preset voltage, and provides a turn-on voltage to a discharge protection circuit to control the discharge protection circuit to provide at least one second discharge path.

Abstract: A method for fabricating the semiconductor device includes providing a substrate, forming a bottom conductive plug on the substrate, forming a semiconductor layer on the bottom conductive plug, rounding a top surface of the semiconductor layer, turning the semiconductor layer into an intervening conductive layer, and forming a top conductive plug on the intervening conductive layer

Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate having a surface. The surface has a first portion and a second portion protruding from the first portion. The semiconductor device also includes a dielectric layer disposed on the second portion and a gate conductive layer disposed on the dielectric layer.

Abstract: The present application provides a semiconductor device with an edge-protecting spacer over a bonding pad. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a dielectric liner disposed between the first spacer and the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the bonding pad and covering the first spacer and the dielectric liner, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.

Abstract: The present application provides a method of manufacturing a memory device having a word line (WL) with improved adhesion between a work function member and a conductive layer. The method includes steps of providing a semiconductor substrate defined with an active area and including an isolation structure surrounding the active area; forming a recess extending into the semiconductor substrate and across the active area; forming a first insulating layer conformal to the recess; disposing a first conductive material conformal to the first insulating layer; forming a conductive member surrounded by the first conductive material; disposing a second conductive material over the conductive member and removing a portion of the first conductive material above the second conductive material to form a conductive layer enclosing the conductive member; and forming a second insulating layer over the conductive layer and conformal to the first insulating layer.

Abstract: The present disclosure provides a semiconductor structure having a bit line with a tapered configuration. The semiconductor structure includes: a substrate; a bit line structure, disposed over the substrate, wherein the bit line structure includes a cylindrical portion and a step portion above the cylindrical portion; a polysilicon layer, disposed over the substrate and around the bit line structure; and a landing pad, disposed over the polysilicon layer and the step portion.

Abstract: The present application discloses a semiconductor device. The semiconductor device includes a package structure including a first side and a second side opposite to the first side; an interposer structure positioned over the first side of the package structure; a first die positioned over the interposer structure; a second die positioned over the interposer structure; and a plurality of middle interconnectors positioned between the first side of the package structure and the first die and between the first side of the package structure and the second die. The plurality of middle interconnectors respectively includes a middle exterior layer positioned between the first side of the package structure and the interposer structure, a middle interior layer enclosed by the middle exterior layer, and a cavity enclosed by the interposer structure, the package structure, and the middle interior layer.

Abstract: The present disclosure provides a semiconductor device with an interconnect part and a method for preparing the semiconductor device. The semiconductor device comprises a device substrate and an interconnect part disposed over the device substrate. The interconnect part includes a lower redistribution layer electrically connected to the backside contact, and an upper redistribution layer disposed over the lower redistribution layer. The interconnect part also includes an interconnect frame disposed between and electrically connected to the lower redistribution layer and the upper redistribution layer. The interconnect part further includes a passivation structure surrounding the interconnect frame.

Abstract: The present disclosure provides a method for preparing a semiconductor device. The method includes forming a sacrificial source/drain structure over a first carrier substrate; forming a redistribution structure over the sacrificial source/drain structure; attaching the redistribution structure to a second carrier substrate; removing the first carrier substrate after the redistribution structure is attached to the second carrier substrate; replacing the sacrificial source/drain structure with a first source/drain structure; forming a backside contact over and electrically connected to the first source/drain structure; and forming an interconnect part over the backside contact.

Abstract: A power voltage supply device, including a reference bias voltage generating circuit, a temperature compensation bias voltage generating circuit, a compensation voltage generator, and a voltage buffer, is provided. The reference bias voltage generating circuit generates a reference bias voltage. The temperature compensation bias voltage generating circuit generates a temperature compensation bias voltage that changes as temperature rises. The compensation voltage generator generates a first power voltage based on the reference bias voltage, and selectively boosts the first power voltage based on the temperature compensation bias voltage. An input terminal of the voltage buffer receives the first power voltage. The voltage buffer generates a second power voltage corresponding to the first power voltage to a load circuit.

Abstract: A voltage generating device includes a clock signal generator, a voltage regulator and a pump circuit. The clock signal generator generates a clock signal according to an enable signal. The voltage regulator generates and adjusts a first voltage according to a reference voltage and the enable signal. The pump circuit receives the clock signal, the first voltage and a second voltage, wherein the pump circuit performs a voltage pump operation to generate an output voltage based on the clock signal according to the first voltage and the second voltage. The output voltage equals to a summation of the first voltage and the second voltage.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate and a conductive pad disposed on the substrate and having a first surface facing away from the substrate. The first surface of the conductive pad is recessed toward the substrate and defines a recessed portion. The semiconductor device also includes a capacitor structure at least partially-disposed within the recessed portion of the conductive pad and electrically connected with the substrate through the conductive pad.

Abstract: The present disclosure provides a semiconductor memory device. The semiconductor memory device comprises a substrate, which includes a storage area and a peripheral area, wherein the storage area has a contact plug, a bit line structure adjacent to the contact plug, an air gap between the bit line structure and the contact plug, a barrier layer conformally overlaying the bit line structure, and a landing pad above the barrier layer, wherein the substrate includes a trench between the storage area and the peripheral area, the trench is filled with a nitride material, and the substrate further comprises a first oxide layer above the nitride material in the trench and on the landing pad, a nitride layer above the first oxide layer, and a second layer above the nitride layer.

Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming an energy-sensitive layer over the target layer. The method also includes performing a first energy treating process to form a first treated portion in the energy-sensitive layer, and performing a second energy treating process to form a second treated portion in the energy-sensitive layer. The method further includes removing the first treated portion and the second treated portion to form a first opening and a second opening in the energy-sensitive layer, and transferring the first opening and the second opening into the target layer.

Abstract: The present application discloses a conductive layer stack, a semiconductor device and methods for fabricating the conductive layer stack and the semiconductor device. The conductive layer stack includes an intervening layer comprising tungsten silicide and positioned on an under-layer; a filler layer comprising tungsten and positioned on the intervening layer. The under-layer comprises titanium nitride and comprises a columnar grain structure. A thickness of the intervening layer is greater than about 4.1 nm.

Abstract: The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a fusion-bonding interface is formed between the first device wafer and the second device wafer, wherein the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.

Abstract: The provides a method for fabricating a semiconductor device including performing a bonding process to bond a second die onto a first die including a pad layer, forming a through-substrate opening along the second die and extending to the pad layer in the first die, conformally forming an isolation layer in the through-substrate opening, performing a punch etch process to remove a portion of the isolation layer and expose a portion of a top surface of the pad layer, performing an isotropic etch process to form a recessed space extending from the through substrate opening and in the pad layer, conformally forming a barrier layer in the through-substrate opening and the recessed space, and forming a filler layer in the through-substrate opening and the recessed space.

Abstract: The present application discloses a semiconductor device. The semiconductor device includes a package structure including a first side and a second side opposite to the first side; an interposer structure positioned over the first side of the package structure; a first die positioned over the interposer structure; a second die positioned over the interposer structure; and a plurality of bottom interconnectors positioned on the second side of the package structure, and respectively including: a bottom exterior layer positioned on the second side of the package structure; a bottom interior layer enclosed by the bottom exterior layer; and a cavity enclosed by the bottom interior layer.