Abstract: Methods, systems, and computer programs for managing storage using a solid state drive (SSD) read cache memory are presented. One method includes an operation for determining whether data corresponding to a read request is available in a SSD memory when the read request causes a miss in a memory cache. The read request is served from the SSD memory when the data is available in the SSD memory, and when the data is not available in the SSD memory, SSD memory tracking logic is invoked and the read request is served from a hard disk drive. Invoking the SSD memory tracking logic includes determining whether a fetch criteria for the data has been met, and loading the data corresponding to the read request in the SSD memory when the fetch criteria has been met. The use of the SSD as a read cache improves memory performance for random data reads.

Abstract: A method of reducing current leakage in unused circuits performed during semiconductor fabrication and a semiconductor device or integrated circuit thereby formed. The method involves modifying a characteristic of at least one idle circuit that is unused in a product variant, to inhibit the circuit and reduce current leakage therefrom upon powering as well as during operation. The method can substantially increase the Vt (threshold voltage) of all transistors of a given type, such as all N-type transistors or all P-type transistors. The method is also suitable for controlling other transistor parameters, such as transistor channel length, as well as other active elements, such as N-type resistors or P-type resistors, in unused circuits which affect leakage current as well as for other unused circuits, such as a high Vt circuit, a standard Vt circuit, a low Vt circuit, and an SRAM cell Vt circuit.

Abstract: A nonvolatile memory controller to recover encoded data by performing a hard-decision inner error correction code decoding and an outer error correction code decoding of the data decoded using the hard-decision inner error correction code decoding and then determining if the encoded data has been successfully decoded. If the encoded data has not been successfully decoded, the controller performs a soft-decision inner error correction code decoding of the encoded data using a soft-decision algorithm and an outer error correction code decoding of the data decoded using the soft-decision inner error correction code decoding and then determining if the encoded data has been successfully decoded. If the encoded data has not been successfully decoded, the controller recovers the data by performing a RAID operation on the encoded data.

Abstract: A method and apparatus, such as multi-engine controller that can be used to control multiple data processing engines in a command based IO processing system, such as a storage controller, to solve to the problem of scaling the data processing rate to match the advances in the IO interface data rates, including a method of identifying dependencies among various tasks queued up in the system and scheduling tasks out-of-order to avoid head of line blocking, a method to buffer and reorder the completed tasks such that the task output order is the same as that in the input to the system.

Abstract: A data regeneration device regenerates a digital signal in a low-speed pass-through mode of operation, performs an upstream link equalization procedure on an upstream data link in an equalization mode of operation, performs a downstream link equalization procedure on a downstream data link in the equalization mode of operation, and regenerates the digital signal in a high-speed pass-through mode of operation. The data regeneration device transitions seamlessly from the low-speed pass-through mode of operation to the equalization mode of operation in compliance with a communication protocol. Moreover, the data regeneration device synchronizes completion of the upstream link equalization procedure with completion of the downstream link equalization procedure so that the data regeneration device transitions seamlessly from the equalization mode of operation to the high-speed pass-through mode of operation in compliance with the communication protocol.

Abstract: A nonvolatile memory controller performs a data stripe operation on data blocks by processing a collection of commands. The nonvolatile memory controller includes command processing units, each of which processes a command of the data stripe operation to store a data block into a nonvolatile memory device. A parity calculator in the nonvolatile memory controller receives the data blocks of the data stripe operation by receiving a sequence of data blocks. The parity calculator generates a parity block in a page frame as the parity calculator receives the sequence of the data blocks. A command processing unit in the nonvolatile memory controller determines when the parity calculator has completed generating the parity block and writes the parity block to a nonvolatile memory device.

Abstract: A multi-mode driver with multiple transmitter types including a first transmitter coupled to a transmission channel and operative to output a signal for transmission on the channel and a second transmitter coupled to the channel and operative to output the signal for transmission on the channel, the second transmitter having at least one different output characteristic than the first transmitter. During the output of the signal from one of the transmitters, the other of the transmitters is biased with a bias supply voltage that prevents voltage breakdown of one or more transistors of the other transmitter.

Abstract: A nonvolatile memory controller includes a host controller interface, processors, a message networks and a data network. The host controller interface includes a command fetch module, command assembly buffers, and a command dispatch module. The command fetch module retrieves nonvolatile memory commands from a host processing unit. The command assembly buffers store the nonvolatile memory commands retrieved from the host processing unit. The command dispatch module generates request message packets including the nonvolatile memory commands. The message network routes the request message packets to the processors. The processors process the nonvolatile memory commands in the request message packets for controlling operation of the nonvolatile memory controller.

Abstract: A method and apparatus for queue-ordering commands in multi-engines, multi-queues and/or multi-flows environment is provided. Commands from single/multiple queues and multi-flows are processed by multi-engines with different processing time and/or out of order, which breaks sequential order of commands from same input queue and commands are distributed across multiple engines' output buffer after processing. Processed commands are stored in dedicated command output buffer associated with each engine temporarily. The processed commands are re-ordered while writing out. Also commands can be scheduled to idle engines to achieve maximum throughput, thus utilizing the engines in an optimal manner.

Abstract: A method and apparatus are described for signaling the phase and frequency of constant bit rate (CBR) clients over a network or fabric. An incoming CBR client stream is segmented into variable sized segments, such as packets or general framing protocol (GFP) frames, and is regenerated on the other side of a fabric or network phase-locked to the incoming stream. Regeneration of the CBR client clock is based solely on segment sizes, and in the case of GFP frames, the rate of the SONET Path or OTN ODUk stream carrying the GFP frames. No overhead bytes are inserted into the GFP frames to convey phase and frequency information. The method disclosed is important for reducing the cost and complexity of communications networks by allowing CBR clients to be transported with low jitter and wander without requiring the source and sink network elements to be phase-locked to a common stratum reference.

Abstract: The present disclosure provides systems and methods for testing an integrated circuit or device under test (DUT). A DUT of the present invention has a plurality of scan chains, a plurality of shift register elements each associated with a respective one of the scan chains, and a programmable switch matrix to configure shift register elements of a subset of the plurality of shift register elements to cause one shift register element of the subset to receive an interleaved test sequence, and to cause the interleaved test sequence to be shifted to other shift register elements in the subset, and to input deinterleaved test sequences to scan chains associated with the subset.

Abstract: A scatter gather cache system and method are provided, which increase performance of scatter-gather DMA operations by reducing the time taken by the DMA engine to perform a logical to physical address translation. This is done primarily by two-dimensional caching of scatter-gather elements of selected scatter-gather lists using a novel indexing, line swapping and replacement methodology. The cache can also include a context victim table (CVT) for storing scatter-gather list contexts from evicted cache entries and also allows for pre-fetching of SGL elements from Scatter-Gather Lists (SGL). It also provides coherency support when there are multiple instances of the cache accessing the same memory space.

Abstract: Methods and apparatus for increasing the number of addressable node ports within one arbitrated loop are provided in a way that allows all node ports be able to participate in loop operations. The method also adds destination filtering based on the source address to determine which of the similarly addressed node ports a message is destined for. A unique arbitrated loop physical address is acquired by a connectivity device. A shared arbitrated loop physical address is acquired by each drive in a set of drives attached to the connectivity device. The shared arbitrated loop physical address is part of a set of shared arbitrated loop physical addresses that are shared among a plurality of connectivity devices. The drive can be uniquely addressed using a pairing of the shared loop physical address associated with the drive and the unique arbitrated loop physical address associated with the selected connectivity device.

Abstract: A method and system are provided for forward error correction. Embodiments of the present disclosure provide a strong FEC algorithm that performs similarly to RS(255,239) when a simple decoder is used, and scales up linearly to a full-scale decoder that outperforms all 7% algorithms currently in G.975.1. The Forward Error Correction code is suitable for use in optical transport networks (OTN) and other applications requiring high decode performance and high code rate. Embodiments of the present disclosure provide an FEC code that is a cyclically interleaved dual BCH, with simultaneous decode and per-codeword maximum likelihood reconciliation.

Abstract: A method to look at the incoming received data on a SerDes link while running in normal operation without requiring a second receive path or any defined or repeated data patterns to be able to generate statistical eye plots both before and after any internal equalization; generate trajectory eye plots both before and after any internal equalization; estimate TED characteristics (hence also estimate SJ jitter tolerance of the link); estimate complete Channel Impulse Response (hence also estimate the S-parameters of the complete channel); and estimate the decomposed jitter of the complete channel.

Abstract: A method and system are provided for forward error correction. Embodiments of the present disclosure provide a strong FEC algorithm that performs similarly to RS(255, 239) when a simple decoder is used, and scales up linearly to a full-scale decoder that outperforms all 7% algorithms currently in G.975.1. The Forward Error Correction code is suitable for use in optical transport networks (OTN) and other applications requiring high decode performance and high code rate. Embodiments of the present disclosure provide an FEC code that is a cyclically interleaved dual BCH, with simultaneous decode and per-codeword maximum likelihood reconciliation.

Abstract: A method and system are provided for forward error correction. Embodiments of the present disclosure provide a strong FEC algorithm that performs similarly to RS(255,239) when a simple decoder is used, and scales up linearly to a full-scale decoder that outperforms all 7% algorithms currently in G.975.1. The Forward Error Correction code is suitable for use in optical transport networks (OTN) and other applications requiring high decode performance and high code rate. Embodiments of the present disclosure provide an FEC code that is a cyclically interleaved dual BCH, with simultaneous decode and per-codeword maximum likelihood reconciliation.

Abstract: A method for simulating a chip is provided. The method initiates with defining a library of components for a processor. Then, the interconnections for a set of pipelined processors including the processor are defined. Next, a processor circuit is generated by combining the library of components and the interconnections for the set of pipelined processors. Then, a code representation of a model of the set of pipelined processors is generated. Next, the signals generated by the code representation are compared to the signals generated by the processor circuit. If the comparison of the signals is unacceptable, then the method includes identifying a cause of the unacceptable comparison of the signals at a block level of the processor circuit. A method for generating a netlist for a pipeline of processors, a method for debugging the processor circuit and computer code for simulating a chip circuit are also provided.

Abstract: A DMA engine is provided that is suitable for higher performance System On a Chip (SOC) devices that have multiple concurrent on-chip/off-chip memory spaces. The DMA engine operates either on logical addressing method or physical addressing method and provides random and sequential mapping function from logical address to physical address while supporting frequent context switching among a large number of logical address spaces. Embodiments of the present invention utilize per direction (source-destination) queuing and an internal switch to support non-blocking concurrent transfer of data on multiple directions. A caching technique can be incorporated to reduce the overhead of address translation.

Abstract: A method and system are provided for forward error correction. Embodiments of the present disclosure provide a strong FEC algorithm that performs similarly to RS(255,239) when a simple decoder is used, and scales up linearly to a full-scale decoder that outperforms all 7% algorithms currently in G.975.1. The Forward Error Correction code is suitable for use in optical transport networks (OTN) and other applications requiring high decode performance and high code rate. Embodiments of the present disclosure provide an FEC code that is a cyclically interleaved dual BCH, with simultaneous decode and per-codeword maximum likelihood reconciliation.