Abstract: A scatter gather element based caching system is provided along with a modified scatter gather element, that supports efficient logical to physical address translation for arbitrarily aligned and arbitrarily sized fragment (segment) based memory management schemes. This is different from modern CPU implementations with MMUs that support page-based implementations. A primary application of embodiments of the present invention is in DMA applications. The system enables frequent switching of contexts between I/Os using a novel caching technique. An embodiment of the present invention also includes the modification of the conventional scatter-gather element used in DMA for supporting multiple memory spaces, backward list traversals, better error recovery and debugging.

Abstract: A system and method for providing redundant access paths to a storage device make use of a processor to analyze instructions received from hosts to allow for command queuing, host switching, and command replacement where necessary. The system allows for either Serially Attached SCSI or Serial ATA hard drives to be connected to the same topology and to require no host intervention on the coordination of drive access in a multi-host environment. A single ported SATA device can then appear multi-ported and can support a redundant architecture within a SAS topology.

Abstract: A Galois Field multiplier circuit for multiplying two polynomials (multiplicands). The multiplier circuit can use any arbitrary primitive polynomial to preserve the Galois Field. The multiplier circuit includes at least one logic unit that receives as a first input one of the multiplicands and shift the multiplicand in question by 1 bit to the left. The logic unit receives as a second input a pre-determined primitive polynomial and multiplies the primitive polynomial by the highest bit of the multiplicand received at the other input of the logic unit. The bit-shifted multiplicand is XOR-ed with the primitive polynomial multiplied the highest bit of the multiplicand and the result of the XOR operation is provided to a second logic circuit that completes the multiplication of the two polynomials.

Abstract: A method and apparatus are provided for implementing connection management in SAS expander devices. SAS expanders are commonly used within a SAS network topology to allow multiple disk drives to connect to multiple host devices. The method and apparatus provides arbitration of connection requests to be setup or removed among multiple end devices and expander devices so as to increase system performance and reduce hardware cost in a standard compliant manner.

Abstract: A method and system are provided for broadcast message filtering in SAS expanders. Common SAS topology defined by ANSI T10 specification only supports spanning tree topology (without loops) interconnection among multiple end devices and expander devices. Broadcast message filtering provides a mechanism to selectively discard broadcast messages, or primitives, in the SAS expanders to break the infinite loop path that broadcast primitives can traverse. This enables new SAS physical topologies with loops that are otherwise difficult or impossible to realize using SAS expanders that handle primitive broadcasts according to the definition of the SAS standard. By allowing redundant paths in a SAS topology, the problem of infinite broadcast flooding in SAS topology is reduced. Selectively forwarding broadcast messages can be based on whether the broadcast was originated at the source phy, or received by the source phy, or based on whether the source phy is a filtered phy.

Abstract: A method and an apparatus for reducing power consumption and digital logic noise in a time division multiplexed memory switch. The method is embodied in an egress selection switch (ESS) block architecture. The ESS block includes a data disable block which prevents the propagation of data, in particular ingress grains, to a given group of egress ports if the data is not selected by any of the egress ports in a given group. While the ingress data disable method partitions ports into groups and saves power by disabling the fanout tree from the root on a port group basis, the egress data disable method saves power on a port group basis by disabling the fanout tree from the tail end in addition to applying the ingress data disable method. The ESS block also includes an grain select block for selecting and storing a given ingress grain for eventual output to an egress port.

Abstract: The invention provides an electrostatic discharge (ESD) protection device for protecting the internal circuitry of an integrated circuit chip from ESD current. The device includes a natively doped substrate having high resistance. A first well is formed in the substrate including a discharge circuit. A second well is formed in the substrate separated from the first well by the width of a natively doped region. The natively doped region has the same connectivity type and substantially the same doping profile as the substrate. During an ESD event, current leaking through the natively doped region between the discharge circuit and the second well creates a voltage that triggers the discharge circuit when reaching its trigger voltage. The resistance ratio between the natively doped region and the well is about 10 times or greater.

Abstract: A method and system for analyzing a signal waveform that comprises digitally sampling a signal at a periodic sampling interval, and accumulating a count of samples of the signal at a given logic level relative to a threshold value over a given period. The threshold value is stepped through a series of values while the accumulating of samples is repeated at a series of different clock offsets. The accumulated counts permit a statistical distribution of the signal waveform to be determined. A signal density can also be calculated by determining the difference between the count of adjacent samples at successive threshold values.

Abstract: An apparatus is disclosed for handling multiple requestors desiring access to a resource. The apparatus includes a plurality of masters and a plurality of arbitrators. Each arbitrator is assigned to a different one of the plurality of masters. Also, each arbitrator is defined to consider a different portion of the multiple requestors when selecting a requestor to be serviced by the master to which the arbitrator is assigned. Each arbitrator is further defined to select a requestor from the different portion of the multiple requestors, such that selection of a particular requestor is not duplicated among the plurality of arbitrators. Additionally, requestor selection by each of the plurality of arbitrators is performed in a same clock cycle.

Abstract: A circuit is provided for handling multiple requestors desiring access to a resource. The circuit includes a plurality of arbitrators and a plurality of masters. Each master is assigned to a different one of the plurality of arbitrators. Each arbitrator is defined to select a different one of the multiple requestors to be serviced by the master to which the arbitrator is assigned. Also, the plurality of arbitrators is defined to make their requestor selections in the same clock cycle. Additionally, the plurality of arbitrators is defined to make their requestor selections such that selection of a particular requestor is not duplicated among the plurality of arbitrators.

Abstract: The present invention provides a novel structure that can be used to filter certain selected frequencies of common mode signals. The structure comprises a stub connected in parallel to a transmission line with termination at the end. It is suitable for implementation on printed circuit boards or backplanes, but it can be also used within the chip, either on die or package substrate. The structure can be also used as an equalizer, and can be used in designing an analog equalizer for high-speed circuits.

Abstract: A method and apparatus are provided for finding the maxima and minima from a set of inputs data. Given a master set K[0 . . . N?1] of N keys, the current invention can pre-compute a comparison matrix, find the maximum key KMAX or minimum key KMIN from the master set K[0 . . . N?1] and indicate the key position index PMAX of the maximum key or PMIN of the minimum key. Given a subset S[0 . . . M?1] of M keys where the subset S[0 . . . M?1] belongs to the master set K[0 . . . N?1], the current invention can also find the maximum key SMAX or minimum key SMIN from the subset S[0 . . . M?1] and indicate the reference key position index PMAX of the maxima SMAX or PMIN of the minima SMIN in the master set K[0 . . . N?1]. The current invention can also find a specific rank of key (example 5th largest key or 6th smallest key) and return the reference key index position in the master set K[0 . . . N?1].

Abstract: Delay measurement and delay calibration methods and apparatus are described for use within distributed wireless base stations employing a remote radio head topology. The methods and apparatus are usable in any system that requires accurate delay measurement and/or constant delay through an electronic device. The methods and apparatus for measuring delay embody a highly accurate distributed delay measurement architecture that handles multiple delay paths within distributed wireless base stations employing a remote radio head topology. The method and apparatus are amenable to implementation with current integrated circuit technology. The methods and apparatus for calibrating electronic delay within distributed base stations employing a remote radio head topology are useful for implementing distributed wireless base stations where transmit diversity is desired.

Abstract: Methods and devices for controlling and managing data flow and data transmission rates. A feedback mechanism is used in conjunction with measuring output transmission rates to control the input transmission rates, changing conditions can be accounted for an excess output transmission capacity can be shared among numerous input ports. Similarly, by using maximum and minimum rates which can be requested from an output port, minimum transmission rates can be guaranteed for high priority traffic while capping maximum output rates for low priority traffic. By combining the two ideas of feedback rate control and placing maximum requestable transmission rates, a more equitable output sharing mechanism arises. The measured output transmission rate is used to control and recalculate the maximum requestable output transmission rate for incoming flows, thereby allowing for changing network and data flow conditions.

Abstract: A networking application processor is provided. The processor includes an input socket configured to receive data packets. The processor includes a memory for holding instructions and circuitry configured to access data structures associated with the processing stages. The circuitry configured to access data structures enables a single cycle access to an operand from a memory location. An arithmetic logic unit (ALU) is provided. Circuitry for aligning operands to be processed by the ALU is included. The circuitry for aligning the operands causes the operand to be aligned by a lowest significant bit, wherein the circuitry for aligning the operand supplies an extension to the operand to allow the ALU to process different size operands.

Abstract: A DMA engine is provided that is suitable for higher performance System On a Chip (SOC) devices that have multiple concurrent on-chip/off-chip memory spaces. The DMA engine operates either on logical addressing method or physical addressing method and provides random and sequential mapping function from logical address to physical address while supporting frequent context switching among a large number of logical address spaces. Embodiments of the present invention utilize per direction (source-destination) queuing and an internal switch to support non-blocking concurrent transfer of data on multiple directions. A caching technique can be incorporated to reduce the overhead of address translation.

Abstract: A method and apparatus are provided for reducing, and preferably substantially eliminating, data-pattern autocorrelations found in digital communication systems. The method employed is referred to as Data Subset Selection (DSS) and is implemented in the form of DSS engine. Autocorrelations in the data-pattern can cause many digital adaptive systems to converge to an incorrect solution. For example, the LMS method, which is often used in adaptive filtering applications, can converge to an incorrect set of filter coefficients in the presence of data-pattern autocorrelations. Digital timing recovery methods are also susceptible. Other impairments that result from data-pattern autocorrelations include increased convergence time and increased steady-state chatter.

Abstract: Methods and apparatus for increasing the number of addressable node ports within one arbitrated loop are provided in a way that allows all node ports be able to participate in loop operations. The method also adds destination filtering based on the source address to determine which of the similarly addressed node ports a message is destined for. A unique arbitrated loop physical address is acquired by a connectivity device. A shared arbitrated loop physical address is acquired by each drive in a set of drives attached to the connectivity device. The shared arbitrated loop physical address is part of a set of shared arbitrated loop physical addresses that are shared among a plurality of connectivity devices. The drive can be uniquely addressed using a pairing of the shared loop physical address associated with the drive and the unique arbitrated loop physical address associated with the selected connectivity device.

Abstract: In one of many embodiments, an InfiniBand network architecture is provided where a router circuitry communicates data between a host and a target device where the router circuitry includes circuitry for generating an external queue pair (QP) for establishing communication between the router circuitry and the host through a reliable connection (RC) session. The router circuitry also includes circuitry for generating internal queue pairs where the internal queue pairs establishes communication between the router circuitry and a device controller, between the between the device controller and the target device, and between the router circuitry and the target device by using reliable connection (RC) sessions. The router circuitry also includes mapping circuitry capable of establishing data destinations in communications between the target and the host. The internal queue pairs are coupled with the external queue pair through the mapping circuitry.

Abstract: An invention is provided for authenticating software associated with an embedded device on a motherboard. An embodiment includes executing an option ROM BIOS for the embedded device. If a bit pattern read from a first memory located on the host card does not match a predetermined bit pattern, the option ROM BIOS is terminated. In another embodiment, a first memory address is provided to the address lines of a memory device located on the host card and a first set of data is output from the memory device, followed by a second memory address to output a second set of data. The second memory address is equal to the first memory address plus the maximum addressable size of the memory device. The first set of data is compared to the second data, and the option ROM BIOS is terminated if the first and second sets of data do not match.