Abstract: The present invention provides a novel structure that can be used to make a common mode filter. Only the common mode will be attenuated and the differential mode will not be attenuated. This structure can be implemented in a number of ways, a specific embodiment using strip-line and slot-line junctions is very compact and well-suited to use with multilayer PCBs, and does not require any extra components. It can be designed to attenuate certain discrete frequencies, by designing the poles of the transfer function to be at these frequencies.

Abstract: A system and method are provided to detect an extended error burst in a data interface. An original error burst has a given length prior to or during transmission. Data transmission processing can extend the original error burst beyond its original length to become an extended error burst with an effective length greater than the original error burst length. Such data transmission processing can include: de-interleaving data on a multi-lane data interface; feedback from a Decision Feedback Equalizer (DFE) receiver; and/or block line decoding, such as 8B/10B block line code decoding. An extended error burst detector can include a suitable error detecting code, such as an r-bit cyclic redundancy check (CRC) code developed in relation to known extended error burst patterns, to detect all extended error bursts based on an up to r-bit original error burst. The detector can also detect error bursts that are not extended beyond the original error burst length.

Abstract: A cache system includes a cache memory dedicated to service a number of sequencers with sequencer code. A number of cache managers are defined to direct placement of sequencer code portions into the cache memory. Also, each of the number of cache managers is defined to provide sequencer code from the cache memory to a respectively assigned sequencer. An external memory is defined to store a complete version of the sequencer code. A direct memory access (DMA) engine is defined to write sequencer code portions from the external memory to the cache memory, in accordance with direction from the number of cache managers.

Abstract: A high-speed rule processing apparatus is disclosed that may be used to implement a wide variety of rule processing tasks such as network address translation, firewall protection, quality of service, IP routing, and/or load balancing. The high-speed rule processor uses an array of compare engines that operate in parallel. Each compare engine includes memory for storing instructions and operands, an arithmetic-logic for performing comparisons, and control circuitry for interpreting the instructions and operands. The results from the array of compare engines is prioritized using a priority encoding system.