Abstract: An integrated circuit package includes a substrate having first and second surfaces and a plurality of conductive traces therebetween and a semiconductor die mounted on the first surface of the substrate. A plurality of wire bonds connect the semiconductor die to ones of the conductive traces of the substrate and an encapsulant encapsulates the wirebonds and the semiconductor die. A heat spreader has a cap, at least a portion of the cap extending inwardly toward and being spaced from the semiconductor die. The encapsulant fills the space between the portion of the cap and the semiconductor die. The heat spreader further has at least one sidewall extending from the cap, the at least one sidewall disposed on the substrate. A ball grid array is disposed on the second surface of the substrate, bumps of the ball grid array being in electrical connection with ones of the conductive traces.

Abstract: A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer.

Abstract: Disclosed is a screen for displaying information for an optical device which is arranged within an optical path of an optical device. The screen for displaying information includes a transparent organic light-emitting diode (TOLED) which emits light in accordance with power and an input control signal.

Abstract: Methods and structures for stack type semiconductor packaging are disclosed. In one embodiment, a semiconductor device includes a semiconductor chip mounted onto a substrate, a first resin molding portion formed on the substrate for sealing the semiconductor chip, and a through metal mounted on the substrate so as to pierce the first resin molding portion around the semiconductor chip. The semiconductor device further comprises an upper metal electrically coupled with the through metal and mounted on the first resin molding portion to extend from the through metal toward the semiconductor chip along an upper surface of the first resin molding portion, where the through metal and the upper metal are formed into an integral structure.

Abstract: Provided are a magnetic sensor and a method of fabricating the same. The magnetic sensor includes: hall elements disposed in a substrate, a protection layer disposed on the substrate, a seed layer disposed on the protection layer, and an integrated magnetic concentrator (IMC) formed on the seed layer, the seed layer and the IMC each having an uneven surface.

Abstract: A magnetoresistive memory element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer having perpendicular magnetic anisotropy, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. A first surface of the first dielectric is in contact with a first surface of the free magnetic layer. The magnetoresistive memory element further includes a second dielectric, having a first surface that is in contact with a second surface of the free magnetic layer, a conductor, including electrically conductive material, and an electrode, disposed between the second dielectric and the conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion including at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.

Abstract: An opening such as a small-diameter via is formed in a semiconductor substrate such as a monocrystalline silicon chip or wafer by a high etch rate process which leaves the opening with a rough interior surface. A smoothing layer such as a polysilicon layer is applied over the interior surfaces of the openings. The smoothing layer presents a surface smoother than the original interior surface. An insulating layer is formed over the smoothing layer or formed from the smoothing layer, and a conductive element such as a metal is formed in the opening. In a variant, a glass-forming material such as BPSG is applied in the opening. The glass-forming material is reflowed to form a glassy insulating layer which presents a smooth surface. The interface between the metal conductive element and the insulating or glassy layer is smooth, which improves mechanical and electrical properties.

Abstract: A system and method employing at least one semiconductor device, or an arrangement of insulating and metal layers, having at least one detecting region which can include, for example, a recess or opening therein, for detecting a charge representative of a component of a polymer, such as a nucleic acid strand proximate to the detecting region, and a method for manufacturing such a semiconductor device. The system and method can thus be used for sequencing individual nucleotides or bases of ribonucleic acid (RNA) or deoxyribonucleic acid (DNA). The semiconductor device includes at least two doped regions, such as two n-typed regions implanted in a p-typed semiconductor layer or two p-typed regions implanted in an n-typed semiconductor layer. The detecting region permits a current to pass between the two doped regions in response to the presence of the component of the polymer, such as a base of a DNA or RNA strand.

Abstract: Exemplary embodiments are directed to devices for attachment to a swinging instrument that generally include a cover, a base, a chassis, and positive and negative electrical contacts. The base includes a fastening portion and a support portion. The chassis supports a printed circuit board. The devices include a cap configured and dimensioned to mate relative to the support portion of the base. The support portion can support the chassis, the printed circuit board, the positive and negative electrical contacts, and the cap. The cover can be configured and dimensioned to detachably interlock relative to the base. In the mated configuration, the cap and the base can form a battery opening configured and dimensioned to receive therethrough a battery. Exemplary embodiments are also directed to methods of device assembly.

Abstract: A sequence of processing steps presented herein is used to embed an optical signal path within an array of nanowires, using only one lithography step. Using the techniques disclosed, it is not necessary to mask electrical features while forming optical features, and vice versa. Instead, optical and electrical signal paths can be created substantially simultaneously in the same masking cycle. This is made possible by a disparity in the widths of the respective features, the optical signal paths being significantly wider than the electrical ones. Using a damascene process, the structures of disparate widths are plated with metal that over-fills narrow trenches and under-fills a wide trench. An optical cladding material can then be deposited into the trench so as to surround an optical core for light transmission.

Abstract: A high-frequency device having a switching circuit including a semiconductor substrate; a first high-frequency input/output terminal; a second high-frequency input/output terminal; a control signal input terminal; a power terminal; a ground terminal; an insulating portion disposed on a main surface of the semiconductor substrate; and a voltage-applying electrode for applying a predetermined positive voltage from the power electrode to the semiconductor substrate, wherein the switching circuit includes a field-effect transistor disposed in an active region of the semiconductor substrate.

Abstract: An array substrate, a method for fabricating the same and a display device are disclosed. The array substrate comprises a display region, at least two common electrode blocks are disposed at a periphery of the display region and conducted via a pixel electrode bridge line pattern.

Abstract: Embodiments of the present invention include a method for manufacturing, and a structure for a thin film solar module. The method of manufacturing includes fabricating a thin film solar cell and fabricating an electronic conversion unit (ECU) on a single substrate. The thin film solar cell has at least one solar cell diode on a substrate. The ECU has at least one transistor on the substrate. The ECU may further comprise a capacitor and an inductor. The ECU is integrated on the substrate monolithically and electrically connected with the thin film solar cell. The ECU and the thin film solar cell interconnect to form a circuit on the substrate. The ECU is electrically connected to a microcontroller on the solar cell module.

Abstract: A semiconductor fin including a single crystalline semiconductor material is formed on a dielectric layer. A semiconductor shell including an epitaxial semiconductor material is formed on all physically exposed surfaces of the semiconductor fin by selective epitaxy, which deposits the semiconductor material only on semiconductor surfaces and not on dielectric surfaces. The epitaxial semiconductor material can be different from the single crystalline semiconductor material, and the semiconductor shell can be bilaterally strained due to lattice mismatch. A fin field effect transistor including a strained channel can be formed. Further, the semiconductor shell can advantageously alter properties of the source and drain regions, for example, by allowing incorporation of more dopants or by facilitating a metallization process.

Abstract: A semiconductor material is patterned to define elongated fins insulated from an underlying substrate. A polysilicon semiconductor material is deposited over and in between the elongated fins, and is patterned to define elongated gates extending to perpendicularly cross over the elongated fins at a transistor channel. Sidewall spacers are formed on side walls of the elongated gates. Portions of the elongated fins located between the elongated gates are removed, along with the underlying insulation, to expose the underlying substrate. One or more semiconductor material layers are then epitaxially grown from the underlying substrate at locations between the elongated gates. The one or more semiconductor material layers may include an undoped epi-layer and an overlying doped epi-layer. The epitaxial material defines a source or drain of the transistor.

Abstract: The present invention relates to phosphorescent organic electroluminescent devices which have a low concentration of the phosphorescent emitter in the emitting layer.

Abstract: A high-electron-mobility transistor (HEMT) device includes a plurality of semiconductor layers formed on a substrate, wherein a two-dimensional electron gas (2DEG) layer is formed in the semiconductor layers; an etch-stop layer formed on the plurality of semiconductor layers; a p-type semiconductor layer pattern formed on the etch-stop layer; and a gate electrode formed on the p-type semiconductor layer pattern.

Abstract: A light emitting device includes a substrate; a first metal film formed on the substrate; a plurality of light emitting elements arranged in a line, each comprising a second metal film on a lower face thereof, each having a quadrilateral outline; and a die bond placed between the first metal film and the second metal films to fix the second metal film on the first metal film. The substrate includes low wettability areas having wettability to the die bond lower than the first metal film. Each of the low wettability areas is disposed between two of the light emitting elements, and each of four sides of the quadrilateral outline is adjacent to the low wettability area different from the low wettability areas adjacent to one of the other three sides.

Abstract: Aspects of the present invention relate to a test photomask and a method for evaluating critical dimension changes in the test photomask. Various embodiments include a test photomask. The test photomask includes a plurality of cells having a varied density pattern. The plurality of cells include a first group of cells arranged along a first line, the first group of cells having a first combined density ratio. The plurality of cells also include a second group of cells arranged along a second line, the second group of cells having a second combined density ratio. In the plurality of cells, the second combined density ratio for the second group of cells is equal to the first combined density ratio of the first group of cells. The varied density pattern is configured to substantially neutralize fogging effects.

Abstract: Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.