Patents Examined by Ajay K Arora
  • Method of forming copper sulfide film for reducing copper oxidization and loss
    Patent number: 9337036
    Abstract: Effects of copper oxide formation in semiconductor manufacture are mitigated by etching with sulfide plasmas. The plasmas form protective copper sulfide films on copper surfaces and prevent copper oxide formation. When copper oxide formation does occur, the sulfide plasmas are able to transform the copper oxide into acceptable or more conductive copper compounds. Non-oxide copper compounds are removed using clear wet strips.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: May 10, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Zusing Yang, Hong-Ji Lee
  • Fin field effect transistor including asymmetric raised active regions
    Patent number: 9324870
    Abstract: Merged and unmerged raised active regions on semiconductor fins can be simultaneously formed on a same substrate by control of growth rates of a deposited semiconductor material on surfaces of the semiconductor fins. In one embodiment, a growth-rate-retarding dopant can be implanted by angled ion implantation onto sidewall surfaces of first semiconductor fins on which retardation of growth rates is desired, while second semiconductor fins are masked by a masking layer. In another embodiment, a growth-rate-enhancing dopant can be implanted by ion implantation onto sidewall surfaces of second semiconductor fins, while first semiconductor fins are masked by a masking layer. The differential growth rates of the deposited semiconductor material can cause raised active regions on the first semiconductor fins to remain unmerged, and raised active regions on the second semiconductor fins to become merged.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: April 26, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz
  • Lighting device with light sources positioned near the bottom surface of a waveguide
    Patent number: 9322973
    Abstract: A device according to embodiments of the invention includes a waveguide, typically formed from a first section of transparent material. A light source is disposed proximate a bottom surface of the waveguide. The light source comprises a semiconductor light emitting diode and a second section of transparent material disposed between the semiconductor light emitting diode and the waveguide. Sidewalls of the second section of transparent material are reflective. A surface to be illuminated is disposed proximate a top surface of the waveguide. In some embodiments, an edge of the waveguide is curved.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: April 26, 2016
    Assignees: Koninklijke Philips N.V., Lumileds LLC
    Inventor: Serge J. Bierhuizen
  • Method for semiconductor self-aligned patterning
    Patent number: 9318412
    Abstract: A method for semiconductor self-aligned patterning includes steps of providing a substrate comprising a first layer and a second layer, wherein the first layer is on top of the second layer; removing a portion of the first layer to form a first pattern; depositing a first conformal layer on the first pattern; depositing a second conformal layer on the first conformal layer; removing a portion of the second conformal layer to expose a portion of the first conformal layer; and thinning the first conformal layer and the second conformal layer alternatively to form a second pattern. A semiconductor self-aligned structure is also provided.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: April 19, 2016
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: An Hsiung Liu, Ya Chih Wang
  • Double gate type thin film transistor and organic light emitting diode display including the same
    Patent number: 9312353
    Abstract: A double gate type thin film transistor includes a first electrode on a substrate; a gate insulating layer on the first gate electrode; a semiconductor layer on the gate insulating layer corresponding to the first gate electrode; an etch stop layer on the semiconductor layer; source and drain electrodes contacting both sides of the semiconductor layer, respectively, and spaced apart from each other on the etch stop layer; a passivation layer on the source and drain electrode; and a second gate electrode on the passivation layer and having a double-layered structure of a transparent electrode and an opaque electrode.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: April 12, 2016
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Woo-Cheol Jeong, Sung-Jun Yun, Ju-Hee Son
  • Mix doping of a semi-insulating Group III nitride
    Patent number: 9306009
    Abstract: Embodiments of a semi-insulating Group III nitride and methods of fabrication thereof are disclosed. In one embodiment, a semi-insulating Group III nitride layer includes a first doped portion that is doped with a first dopant and a second doped portion that is doped with a second dopant that is different than the first dopant. The first doped portion extends to a first thickness of the semi-insulating Group III nitride layer. The second doped portion extends from approximately the first thickness of the semi-insulating Group III nitride layer to a second thickness of the semi-insulating Group III nitride layer. In one embodiment, the first dopant is Iron (Fe), and the second dopant is Carbon (C). In another embodiment, the semi-insulating Group III nitride layer is a semi-insulating Gallium Nitride (GaN) layer, the first dopant is Fe, and the second dopant is C.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: April 5, 2016
    Assignee: Cree, Inc.
    Inventors: Christer Hallin, Saptharishi Sriram
  • Thin film transistor
    Patent number: 9306075
    Abstract: A thin film transistor including an oxide semiconductor with favorable electrical characteristics is provided. The thin film transistor includes a gate electrode provided over a substrate, a gate insulating film provided over the gate electrode, an oxide semiconductor film provided over the gate electrode and on the gate insulating film, a metal oxide film provided on the oxide semiconductor film, and a metal film provided on the metal oxide film. The oxide semiconductor film is in contact with the metal oxide film, and includes a region whose concentration of metal is higher than that of any other region in the oxide semiconductor film (a high metal concentration region). In the high metal concentration region, the metal contained in the oxide semiconductor film may be present as a crystal grain or a microcrystal.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: April 5, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akiharu Miyanaga, Junichiro Sakata, Masayuki Sakakura, Masahiro Takahashi, Hideyuki Kishida, Shunpei Yamazaki
  • Glass pattern and method for forming the same, sealed body and method for manufacturing the same, and light-emitting device
    Patent number: 9299943
    Abstract: A glass pattern that can be used for a substrate provided with a material having low heat resistance and has increased productivity is provided. Further, a sealed body having high hermeticity and increased productivity is provided. Furthermore, a light-emitting device with high reliability including such a sealed body is provided. A glass sheet is used for a main portion of a glass pattern such as a straight line portion and a curved portion. In a joint portion of two glass sheets arranged in the corner portion, the straight line portion, or the like of the glass pattern, a frit paste is provided in contact with the glass sheets and is locally heated to remove the binder from the frit paste and to form a glass layer; thus, the glass sheets are fused to each other without any space provided therebetween.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: March 29, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Kensuke Yoshizumi
  • Double patterning method of forming semiconductor active areas and isolation regions
    Patent number: 9293358
    Abstract: A method of forming active areas and isolation regions in a semiconductor substrate using a double patterning process. The method include forming a first material on the substrate surface, forming a second material on the first material, forming a plurality of first trenches into the second material wherein the plurality of first trenches are parallel to each other, forming a second trench into the second material wherein the second trench is perpendicular to and crosses the plurality of first trenches in a central region of the substrate, filling the first and second trenches with a third material, removing the second material to form third trenches in the third material that are parallel to each other and do not extend through the central region of the substrate, and extending the third trenches through the first material and into the substrate.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: March 22, 2016
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Jeng-Wei Yang, Chien-Sheng Su
  • Semiconductor switching device separated by device isolation
    Patent number: 9293502
    Abstract: A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: March 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen, Wei-Cheng Hsu, Hsiao-Hui Tseng
  • Optoelectronic component and method for producing an optoelectronic component
    Patent number: 9293671
    Abstract: An optoelectronic component comprising an optoelectronic semiconductor chip (104) having a contact side (106) and a radiation coupling-out side (108) situated opposite; a chip carrier (102), on which the semiconductor chip (104) is applied via its contact side (106); a radiation conversion element (110) applied on the radiation coupling-out side (108); and a reflective potting compound (112), which is applied on the chip carrier (102) and laterally encloses the semiconductor chip (104) and the radiation conversion element (110); wherein the potting compound (112) adjoins an upper edge of the radiation conversion element (110) in a substantially flush fashion, such that a top side of the radiation conversion element (110) is free of the potting compound (112).
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: March 22, 2016
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Herbert Brunner, Hans-Christoph Gallmeier, Simon Jerebic, Stephan Preuβ, Hansjörg Schöll
  • Practical method of producing an aerogel composite continuous thin film thermoelectric semiconductor material by modified MOCVD
    Patent number: 9276190
    Abstract: A method is disclosed of constructing a composite material structure, comprised of an aerogel substrate, which is then overlaid throughout its interior with an even and continuous thin layer film of doped thermoelectric semiconductor such that electrical current is transmitted as a quantum surface phenomena, while the cross-section for thermal conductivity is kept low, with the aerogel itself dissipating that thermal conductivity. In one preferred embodiment this is achieved using a modified metal-organic chemical-vapor deposition (MOCVD) process in the gas phase, with the assist of microwave heating after the reactant gases have evenly diffused throughout the interior of the aerogel substrate.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: March 1, 2016
    Inventor: The Pen
  • Method and apparatus for high yield contact integration scheme
    Patent number: 9275889
    Abstract: A methodology for forming contact areas by a multiple patterning process that provides increased yield and lower risk of contact-to-contact short at points of tight tip-to-tip spacing and the resulting device are disclosed. Embodiments include forming one or more trench patterning layers on a planarized surface of a wafer, forming one or more trenches in the one or more trench patterning layers, forming a block mask at one or more points along the one or more trenches, extending the one or more trenches down to a substrate level of the wafer, and removing the block mask from the one or more points.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: March 1, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ryan Kim, Jason R. Cantone, Wenhui Wang
  • High-electron-mobility transistor
    Patent number: 9269790
    Abstract: A high-electron-mobility transistor (HEMT) device includes a plurality of semiconductor layers formed on a substrate, wherein a two-dimensional electron gas (2DEG) layer is formed in the semiconductor layers; an etch-stop layer formed on the plurality of semiconductor layers; a p-type semiconductor layer pattern formed on the etch-stop layer; and a gate electrode formed on the p-type semiconductor layer pattern.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: February 23, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-hoon Lee, Chan-ho Park, Nam-young Lee
  • Semiconductor device and method of fabricating same
    Patent number: 9269806
    Abstract: A lateral drain metal oxide semiconductor (LDMOS) device includes a well region having a second conductive type in a substrate, a body region having a first conductive type in the well region, a drift region having the second conductive type in the well region and spaced apart from the body region, a source region having the second conductive type in the body region, a drain region having the second conductive type in the drift region, a gate structure on the well region between the source region and the drain region, a shallow trench isolation (STI) structure in the drift region between the drain region and the source region, and a buried layer having the first conductive type in the well region under the drift region, a center of the buried layer being aligned with a center of the STI structure.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: February 23, 2016
    Assignee: Macronix International Co., Ltd.
    Inventors: Jiun-Yan Tsai, Shuo-Lun Tu, Shih-Chin Lien, Shyi-Yuan Wu
  • Gate recessed FDSOI transistor with sandwich of active and etch control layers
    Patent number: 9269804
    Abstract: The structure and the fabrication methods herein implement a fully depleted, recessed gate silicon-on-insulator (SOI) transistor with reduced access resistance, reduced on-current variability, and strain-increased performance. This transistor is based on an SOI substrate that has an epitaxially grown sandwich of SiGe and Si layers that are incorporated in the sources and drains of the transistors. Assuming a metal gate last complementary metal-oxide semiconductor (CMOS) technology and using the sidewall spacers as a hard mask, a recess under the sacrificial gate reaching all the way through the SiGe layer is created, and the high-K gate stack and metal gate are formed within that recess. The remaining Si region, having a precisely controlled thickness, is the fully depleted channel.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: February 23, 2016
    Assignee: SemiWise Limited
    Inventor: Asen Asenov
  • Fluctuation resistant low access resistance fully depleted SOI transistor with improved channel thickness control and reduced access resistance
    Patent number: 9263568
    Abstract: The structure, and fabrication method thereof, implements a fully depleted silicon-on-insulator (SOI) transistor using a “Channel Last” procedure in which the active channel is a low-temperature epitaxial layer in an etched recess in the SOI silicon film. An optional ?-layer of extremely high doping allows its threshold voltage to be set to a desired value. Based on high-K metal gate last technology, this transistor has reduced threshold uncertainty and superior source and drain conductance. The use of epitaxial layer improves the thickness control of the active channel and reduces the process induced variations. The utilization of active silicon layer that is two or more times thicker than those used in conventional fully depleted SOI devices, reduces the access resistance and improves the on-current of the SOI transistor.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: February 16, 2016
    Assignee: SemiWise Limited
    Inventor: Asen Asenov
  • Semiconductor device with buried metal layer
    Patent number: 9263448
    Abstract: A semiconductor device includes: a first active region defined by a recess contained in a device isolation film of a semiconductor substrate belonging to a first region and a second region, in a peripheral region including the first region, the second region, and a third region; a second active region defined by the device isolation film contained in the semiconductor substrate of the third region; a buried metal layer buried in the recess; a first conductive layer formed over the semiconductor substrate of the first region; and a second conductive layer formed over the semiconductor substrate of the second region, wherein the first conductive layer or the second conductive layer is formed over the semiconductor substrate of the third region. A three-dimensional dual gate is formed in a peripheral region, such that performance or throughput of transistors is maximized even in the peripheral region.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: February 16, 2016
    Assignee: SK HYNIX INC.
    Inventors: Min Soo Yoo, Yun Ik Son
  • Semiconductor component and method of triggering avalanche breakdown
    Patent number: 9263619
    Abstract: A semiconductor component includes an auxiliary semiconductor device configured to emit radiation. The semiconductor component further includes a semiconductor device. An electrical coupling and an optical coupling between the auxiliary semiconductor device and the semiconductor device are configured to trigger emission of radiation by the auxiliary semiconductor device and to trigger avalanche breakdown in the semiconductor device by absorption of the radiation in the semiconductor device. The semiconductor device includes a pn junction between a first layer of a first conductivity type buried below a surface of a semiconductor body and a doped semiconductor region of a second conductivity type disposed between the surface and the first layer.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: February 16, 2016
    Assignee: Infineon Technologies AG
    Inventors: Joost Willemen, Michael Mayerhofer, Ulrich Glaser, Yiqun Cao, Andreas Meiser, Magnus-Maria Hell, Matthias Stecher, Julien Lebon
  • CMOS-MEMS integrated flow for making a pressure sensitive transducer
    Patent number: 9254997
    Abstract: A sensor is made up of two substrates which are adhered together. A first substrate includes a pressure-sensitive micro-electrical-mechanical (MEMS) structure and a conductive contact structure that protrudes outwardly beyond a first face of the first substrate. A second substrate includes a complementary metal oxide semiconductor (CMOS) device and a receiving structure made up of sidewalls that meet a conductive surface which is recessed from a first face of the second substrate. A conductive bonding material physically adheres the conductive contact structure to the conductive surface and electrically couples the MEMS structure to the CMOS device.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: February 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Wen Cheng, Kai-Chih Liang, Chia-Hua Chu