Abstract: A semiconductor fin including a single crystalline semiconductor material is formed on a dielectric layer. A semiconductor shell including an epitaxial semiconductor material is formed on all physically exposed surfaces of the semiconductor fin by selective epitaxy, which deposits the semiconductor material only on semiconductor surfaces and not on dielectric surfaces. The epitaxial semiconductor material can be different from the single crystalline semiconductor material, and the semiconductor shell can be bilaterally strained due to lattice mismatch. A fin field effect transistor including a strained channel can be formed. Further, the semiconductor shell can advantageously alter properties of the source and drain regions, for example, by allowing incorporation of more dopants or by facilitating a metallization process.

Abstract: A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.

Abstract: A method of triggering avalanche breakdown in a semiconductor device includes providing an electrical coupling and an optical coupling between an auxiliary semiconductor device configured to emit radiation and the semiconductor device including a pn junction between a first layer of a first conductivity type buried below a surface of a semiconductor body and a doped semiconductor region of a second conductivity type disposed between the surface and the first layer. The electrical and optical coupling includes triggering emission of radiation by the auxiliary semiconductor device and triggering avalanche breakdown in the semiconductor device by absorption of the radiation in the semiconductor device.

Abstract: A semiconductor structure that includes crystalline surfaces and amorphous hydrophilic surfaces is provided. The hydrophilic surfaces are treated with silane that includes a hydrophobic functional group, converting the hydrophilic surfaces to hydrophobic surfaces. Chemical vapor deposition or other suitable deposition methods are used to simultaneously deposit a material on both surfaces and due to the surface treatment, the deposited material exhibits superior adherence qualities on both surfaces. In one embodiment, the structure is an opening formed in a semiconductor substrate and bounded by at least one portion of a crystalline silicon surface and at least one portion of an amorphous silicon oxide structure.

Abstract: The present invention provides an organic light emitting diode display panel and a display device, and relates to the field of display technology, which can solve the problem that the display contrast of an existing organic light emitting diode display panel and an existing display device is reduced due to the reflection of ambient light. In the organic light emitting diode display panel and the display device of the present invention, a light gathering unit and a light absorption layer matched with each other are arranged in pixel defining regions, so that the incident ambient light can be gathered by the light gathering unit to the light absorption layer and absorbed by the light absorption layer, to reduce ambient light outgoing from the display panel due to reflection, and increase the contrast of the display panel.

Abstract: The present disclosure provides a test structure which includes an SOI substrate having an active semiconductor layer, a buried insulating material layer, and a base substrate, wherein the active semiconductor layer is formed on the buried insulating material layer, which, in turn, is formed on the base substrate. The test structure further includes a contact which is formed on the active semiconductor layer and electrically coupled to the active semiconductor layer. Herein, the contact has a tip portion extending through the active semiconductor layer into the buried insulating material layer.

Abstract: A semiconductor device includes: a first active region defined by a recess contained in a device isolation film of a semiconductor substrate belonging to a first region and a second region, in a peripheral region including the first region, the second region, and a third region; a second active region defined by the device isolation film contained in the semiconductor substrate of the third region; a buried metal layer buried in the recess; a first conductive layer formed over the semiconductor substrate of the first region; and a second conductive layer formed over the semiconductor substrate of the second region, wherein the first conductive layer or the second conductive layer is formed over the semiconductor substrate of the third region. A three-dimensional dual gate is formed in a peripheral region, such that performance or throughput of transistors is maximized even in the peripheral region.

Abstract: Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICS, improvement in refresh time for DRAM's, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFET's, and a host of other applications.

Abstract: A trench comprising a portion of a substrate is formed. A nucleation layer is deposited on the portion of the substrate within the trench. A III-N material layer is deposited on the nucleation layer. The III-N material layer is laterally grown over the trench. A device layer is deposited on the laterally grown III-N material layer. A low defect density region is obtained on the laterally grown material and is used for electronic device fabrication of III-N materials on Si substrates.

Abstract: A mechanism to attach a die to a substrate and method of use are disclosed. The vacuum carrier includes a frame composed of material compatible with solder reflow process. The vacuum carrier further includes a vacuum port extending from a top surface to an underside surface of the frame. The vacuum carrier further includes a seal mechanism provided about a perimeter on the underside surface of the frame of the vacuum carrier. The frame and seal mechanism are structured to maintain a flatness of a die attached to the vacuum carrier by a vacuum source during the solder reflow process.

Abstract: A method of controlling polishing includes polishing a region of a substrate at a first polishing rate, measuring a sequence of characterizing values for the region of the substrate during polishing with an in-situ monitoring system, determining a polishing rate adjustment for each of a plurality of adjustment times prior to a polishing endpoint time, and adjusting a polishing parameter to polish the substrate at a second polishing rate. The time period is greater than a period between the adjustment times and the projected time is before the polishing endpoint time. The second polishing rate is the first polishing rate as adjusted by the polishing rate adjustment.

Abstract: Semiconductor devices and methods for forming the devices with spacer chamfering. One method includes, for instance: obtaining a wafer with at least one source, at least one drain, and at least one fin; forming at least one sacrificial gate with at least one barrier layer; forming a first set of spacers adjacent to the at least one sacrificial gate; forming at least one second set of spacers adjacent to the first set of spacers; and etching to remove a portion of the first set of spacers above the at least one barrier layer to form a widened opening. An intermediate semiconductor device is also disclosed.

Abstract: A method is disclosed which cuts hard mask fins thinner than the target fin critical dimension and then enlarges the dimension of the fin hard mask critical dimension to meet the target fin critical dimension.

Abstract: The present disclosure provides an embodiment of a micro-electro-mechanical system (MEMS) structure, the MEMS structure comprising a MEMS substrate; a first and second conductive plugs of a semiconductor material disposed on the MEMS substrate, wherein the first conductive plug is configured for electrical interconnection and the second conductive plug is configured as an anti-stiction bump; a MEMS device configured on the MEMS substrate and electrically coupled with the first conductive plug; and a cap substrate bonded to the MEMS substrate such that the MEMS device is enclosed therebetween.

Abstract: A method of forming contacts for a semiconductor device structure comprises forming contact holes extending into neighboring semiconductive pillars and into a nitride material of nitride-capped electrodes. Composite structures are formed within the contact holes and comprise oxide structures over sidewalls of the contact holes and nitride structures over the oxide structures. Conductive structures are formed over inner sidewalls of the composite structures. Additional nitride-capped electrodes are formed over the conductive structures and extend perpendicular to the nitride-capped electrodes. Pairs of nitride spacers are formed over opposing sidewalls of the additional nitride-capped electrodes and are separated from neighboring pairs of nitride spacers by apertures extending to upper surfaces of a portion of the neighboring semiconductive pillars. Portions of the oxide structures are removed to expose sidewalls of the portion of the neighboring semiconductive pillars.

Abstract: A semiconductor device and method of formation are provided. A semiconductor device includes a first material comprising STI adjacent a fin. The STI is substantially uniform, such that a top surface of the STI has few to no defects and little to no concavity. To form the STI, the first material is implanted with a dopant, which forms an etch stop layer, such that the first material height is reduced by etching rather than CMP. Etching results in a better uniformity of the first material than CMP. STI that is substantially uniform comprises a better current barrier between adjacent fins than a device that comprises STI that is not substantially uniform.

Abstract: A magnetoresistive memory element (for example, a spin-torque magnetoresistive memory element), includes first and second dielectric layers, wherein at least one of the dielectric layers is a magnetic tunnel junction. The memory element also includes a free magnetic layer having a first surface in contact with the first dielectric layer and a second surface in contact with the second dielectric layer. The free magnetic layer, which is disposed between the first and second dielectric layers, includes (i) a first high-iron interface region located along the first surface of the free magnetic layer, wherein the first high-iron interface region has at least 50% iron by atomic composition, and (ii) a first layer of ferromagnetic material adjacent to the first high-iron interface region, the first high-iron interface region between the first layer of ferromagnetic material and the first surface of the free magnetic layer.

Abstract: Merged and unmerged raised active regions on semiconductor fins can be simultaneously formed on a same substrate by control of growth rates of a deposited semiconductor material on surfaces of the semiconductor fins. In one embodiment, a growth-rate-retarding dopant can be implanted by angled ion implantation onto sidewall surfaces of first semiconductor fins on which retardation of growth rates is desired, while second semiconductor fins are masked by a masking layer. In another embodiment, a growth-rate-enhancing dopant can be implanted by ion implantation onto sidewall surfaces of second semiconductor fins, while first semiconductor fins are masked by a masking layer. The differential growth rates of the deposited semiconductor material can cause raised active regions on the first semiconductor fins to remain unmerged, and raised active regions on the second semiconductor fins to become merged.

Abstract: Substrates and packages for LED-based light devices can significantly improve thermal performance and provide separate electrical and thermal paths through the substrate. One substrate includes multiple electrically insulating base layers. On a top one of these layers are disposed top-side electrical contacts, including light device pads to accommodate a plurality of light devices. External electrical contacts are disposed on an exterior surface of the substrate. Electrical paths connect the top-side electrical contacts to the external electrical contacts. At least portions of some of the electrical paths are disposed between the electrically insulating base layers. The electrical paths can be arranged such that different subsets of the light device pads are addressable independently of each other. A heat dissipation plate can be formed on the bottom surface of a bottom one of the base layers.

Abstract: A pixel electrode of an array substrate is connected with a drain electrode of a TFT via a first aperture formed on a second interlayer insulating film, a second aperture that includes a bottom portion of the first aperture and is formed on a common electrode, a third aperture that includes at least a part of the bottom portion of the first aperture, is included in a second aperture and is formed on a third interlayer insulating film, and a fourth aperture that is formed on the first interlayer insulating film in a region where the third aperture overlaps with the bottom portion of the first aperture.