Abstract: A substrate for an LED assembly can have a plurality of cups formed therein. At least one cup can be formed within another cup. The cups can be co-axial with respect to one another, for example. A machined surface of the substrate can enhance reflectivity of the LED assembly. A transparent and/or non-global solder mask can enhance reflectivity of the LED assembly. A transparent ring can enhance reflectivity of the LED assembly. By enhancing reflectivity of the LED assembly, the brightness of the LED assembly can be increased. Brighter LED assemblies can be used in applications such as flashlights, displays, and general illumination.

Abstract: An electronic circuit according to this invention includes a printed circuit board and an electronic component that is soldered onto the printed circuit board. The electronic component is a flat package including a die pad exposed to outside and external electrode terminals. A gap is provided between the printed circuit board and the electronic component. The printed circuit board is provided with a hole between the die pad and the external electrode terminals in planar view. The gap is filled with insulating resin at least partially between the die pad and the external electrode terminals. The insulating resin is injected through the hole.

Abstract: An organic light emitting device includes a substrate, a first electrode disposed on the substrate, a first organic layer pattern disposed on the first electrode, an auxiliary electrode pattern alternately disposed with the first organic layer pattern, and including an upper insulation layer, a lower insulation layer, and an auxiliary electrode disposed therebetween, a light emitting layer disposed on the first organic layer pattern and the auxiliary electrode pattern, a second organic layer disposed on the light emitting layer and a second electrode disposed on the second organic layer.

Abstract: Memory devices and methods of fabricating the same include a substrate including a cell region and a peripheral circuit region, data storages on the cell region, first bit lines on and coupled to the data storages, first contacts coupled to peripheral transistors on the peripheral circuit region, and second bit lines on and coupled to the first contacts. The second bit lines may each have a lowermost surface lower than a lowermost surface of the data storages.

Abstract: An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; a P-well formed on the substrate and having N-type transistors of a memory cell; and an N-well formed on the substrate and having P-type transistors of the memory cell; wherein the N-well has minimal dimensions for accommodating the P-type transistors.

Abstract: A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer.

Abstract: A system and method employing at least one semiconductor device, or an arrangement of insulating and metal layers, having at least one detecting region which can include, for example, a recess or opening therein, for detecting a charge representative of a component of a polymer, such as a nucleic acid strand proximate to the detecting region, and a method for manufacturing such a semiconductor device. The system and method can thus be used for sequencing individual nucleotides or bases of ribonucleic acid (RNA) or deoxyribonucleic acid (DNA). The semiconductor device includes at least two doped regions, such as two n-typed regions implanted in a p-typed semiconductor layer or two p-typed regions implanted in an n-typed semiconductor layer. The detecting region permits a current to pass between the two doped regions in response to the presence of the component of the polymer, such as a base of a DNA or RNA strand.

Abstract: An integrated circuit (IC) die has a top side surface providing circuitry including active circuitry configured to provide a function, including at least one bond pad formed from a bond pad metal coupled to a node in the circuitry. A dielectric passivation layer is over a top side surface of a substrate providing a contact area which exposes the bond pad. A metal capping layer includes an electrically conductive metal or an electrically conductive metal compound over at least the contact area to provide corrosion protection to the bond pad metal, which is in electrical contact with the bond pad metal. The metal capping layer can extend over structures other than the bond pads, such as to cover at least 80% of the area of the IC die to provide structures on the IC die protection from incident radiation.

Abstract: Disclosed are semiconductor structures with monocrystalline semiconductor fins, which are above a trench isolation region in a semiconductor substrate and which can be incorporated into semiconductor device(s). Also disclosed are methods of forming such structures by forming sidewall spacers on opposing sides of mandrels on a dielectric cap layer. Between adjacent mandrels, an opening is formed that extends vertically through the dielectric cap layer and through multiple monocrystalline semiconductor layers into a semiconductor substrate. A portion of the opening within the substrate is expanded to form a trench. This trench undercuts the semiconductor layers and extends laterally below adjacent sidewall spacers on either side of the opening. The trench is then filled with an isolation layer, thereby forming a trench isolation region, and a sidewall image transfer process is performed using the sidewall spacers to form a pair of monocrystalline semiconductor fins above the trench isolation region.

Abstract: High resolution active matrix structures are fabricated using techniques applicable to flexible substrates. A backplane layer including active semiconductor devices is formed using a semiconductor-on-insulator substrate. The substrate is thinned using a layer transfer technique or chemical/mechanical processing. Driver transistors are formed on the semiconductor layer of the substrate along with additional circuits that provide other functions such as computing or sensing. Contacts to passive devices such as organic light emitting diodes may be provided by heavily doped regions formed in the handle layer of the substrate and then isolated. A gate dielectric layer may be formed on the semiconductor layer, which functions as a channel layer, or the insulator layer of the substrate may be employed as a gate dielectric layer.

Abstract: To give stable electrical characteristics to and improve reliability of a semiconductor device including a transistor in which an oxide semiconductor film is used for a channel formation region. As a base film, an insulating film or an oxide semiconductor film is used. A single-layer metal film is formed over the base film. After that, a resist mask is formed, and etching is performed plural times. Accordingly, electrodes each including projecting portions when seen in cross-section are formed. Even when a gate insulating film over the source electrode layer and the drain electrode layer or an oxide semiconductor film has a small thickness, disconnection of the gate insulating film is unlikely to occur.

Abstract: A semiconductor structure that includes crystalline surfaces and amorphous hydrophilic surfaces is provided. The hydrophilic surfaces are treated with silane that includes a hydrophobic functional group, converting the hydrophilic surfaces to hydrophobic surfaces. Chemical vapor deposition or other suitable deposition methods are used to simultaneously deposit a material on both surfaces and due to the surface treatment, the deposited material exhibits superior adherence qualities on both surfaces. In one embodiment, the structure is an opening formed in a semiconductor substrate and bounded by at least one portion of a crystalline silicon surface and at least one portion of an amorphous silicon oxide structure.

Abstract: An e-fuse is provided in one area of a semiconductor substrate. The E-fuse includes a vertical stack of from, bottom to top, base metal semiconductor alloy portion, a first metal semiconductor alloy portion, a second metal semiconductor portion, a third metal semiconductor alloy portion and a fourth metal semiconductor alloy portion, wherein the first metal semiconductor alloy portion and the third metal semiconductor portion have outer edges that are vertically offset and do not extend beyond vertical edges of the second metal semiconductor alloy portion and the fourth metal semiconductor alloy portion.

Abstract: A sealed structure with high sealing capability, in which a pair of substrates is attached to each other with a glass layer is provided. The sealed structure has a first and second substrates, a first surface of the first substrate facing a first surface of the second substrate, and the glass layer which is in contact with the first and second substrates, defines a space between the first and second substrates, and is provided along the periphery of the first surface of the first substrate. The first substrate has a corner portion. The area of the first surface of the first substrate is smaller than or equal to that of the first surface of the second substrate. In at least one of respective welded regions between the glass layer and the first or second substrate, the width of the corner portion is larger than that of the side portion.

Abstract: Provided is a semiconductor device in which generation of a parasitic channel in an end region of an oxide semiconductor film is suppressed. The semiconductor device includes a gate electrode, an oxide semiconductor film, a source electrode and a drain electrode, and a channel region formed in the oxide semiconductor film. The channel region is formed between a first side surface of the source electrode and a second side surface of the drain electrode opposite to the first side surface. The oxide semiconductor film has an end region which does not overlap with the gate electrode. The end region which does not overlap with the gate electrode is positioned between a first region that is the nearest to one end of the first side surface and a second region that is the nearest to one end of the second side surface.

Abstract: Embodiments of the subject invention relate to a method and apparatus for providing a apparatus that can function as a photovoltaic cell, for example during the day, and can provide solid state lighting, for example at night. The apparatus can therefore function as a lighting window. An embodiment can integrate an at least partially transparent one-side emitting OLED and a photovoltaic cell. The photovoltaic cell can be sensitive to infrared light, for example light having a wavelength greater than 1 ?m. The apparatus can be arranged such that the one direction in which the OLED emits is toward the inside of a building or other structure and not out into the environment.

Abstract: The structure, and fabrication method thereof, implements a fully depleted silicon-on-insulator (SOI) transistor using a “Channel Last” procedure in which the active channel is a low-temperature epitaxial layer in an etched recess in the SOI silicon film. A highly localized ion implantation is used to set the threshold voltage of the transistor and to improve the short channel behavior of the final device. Based on high-K metal gate technology, this transistor has reduced threshold uncertainty and superior source and drain conductance.

Abstract: Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICS, improvement in refresh time for DRAM's, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFET's, and a host of other applications.

Abstract: A method for fabricating a fin-type field-effect transistor (FinFET) device includes receiving a precursor. The precursor has a plurality of fins over a substrate and a dielectric layer filling in a space between each of fins and extending above the fins. The method also includes forming a patterned hard mask layer having an opening over the dielectric layer, etching the dielectric layer through the opening to form a trench with vertical profile. A subset of the fins is exposed in the trench. The method also includes performing an isotropic dielectric etch to enlarge the trench in a horizontal direction. The method also includes performing an anisotropic etch to recess the subset of fins in the trench and performing an isotropic fin etch to etch the recessed subset of fins.

Abstract: A chip package device includes an electrically conducting chip carrier, at least one semiconductor chip attached to the electrically conducting chip carrier, and an insulating laminate structure embedding the chip carrier, the at least one semiconductor chip and a passive electronic device. The passive electronic device includes a first structured electrically conducting layer, the first structured electrically conducting layer extending over a surface of the laminate structure.