Patents Examined by Ajay K Arora
  • Structure of backside copper metallization for semiconductor devices and a fabrication method thereof
    Patent number: 9548276
    Abstract: An improved structure of backside copper metallization for semiconductor devices and a fabrication method thereof, wherein the improved structure comprises sequentially from top to bottom an active layer, a substrate, a backside metal seed layer, a high-temperature sustaining buffer layer, a backside metal layer and at least one oxidation resistant layer, wherein the backside metal seed layer contains Pd and P, the high-temperature sustaining buffer layer is made of Ni, Ag or Ni alloys, and the backside metal layer is made of Cu. The semiconductor chip using the structure provided by the present invention can sustain high-temperature operations.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: January 17, 2017
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Jason Chen, Chang-Hwang Hua, Wen Chu
  • OLED device and manufacturing method thereof and display apparatus
    Patent number: 9543539
    Abstract: An OLED device and a manufacturing method thereof and a display apparatus are provided. The OLED device comprises: a substrate, and a first electrode, an organic material function layer and a second electrode which are sequentially provided on the substrate. The OLED device further comprises an uneven layer provided between the first electrode and the substrate, and a surface of the uneven layer corresponding to the first electrode and away from the substrate is not even. The first electrode and/or the second electrode provided on a light output side of the OLED device comprise(s) a metal layer.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: January 10, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Wenyu Ma
  • Organic light-emitting diode display device and its manufacturing method
    Patent number: 9525013
    Abstract: The present disclosure provides an OLED display device and its manufacturing method. The OLED display device includes an anode layer, a cathode layer, and a pixel-defined layer and a light-emitting layer both arranged between the anode layer and the cathode layer. The pixel-defined layer is provided with an opening, and the light-emitting layer is arranged in the opening. An insulating layer having a refractive index greater than that of the pixel-defined layer is arranged between the light-emitting layer and the pixel-defined layer.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: December 20, 2016
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiaowei Xu, Lei Shi, Wenqing Xu
  • 3-D non-volatile memory device and method of manufacturing the same
    Patent number: 9515074
    Abstract: A three-dimensional (3-D) non-volatile memory device includes a plurality of word line structures extended in parallel and including a plurality of interlayer dielectric layers and a plurality of word lines that are alternately stacked over a substrate, a plurality of channels protruding from the substrate configured to penetrate the plurality of interlayer dielectric layers and the plurality of word lines, and an air gap formed between the plurality of word line structures.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: December 6, 2016
    Assignee: SK Hynix Inc.
    Inventors: Sung Jin Whang, Ki Hong Lee
  • Semiconductor light emitting devices with optical coatings and methods of making same
    Patent number: 9515229
    Abstract: A method of making a semiconductor light emitting device having one or more light emitting surfaces includes positioning a stencil on a substrate such that a chip disposed on the substrate is positioned within an opening in the stencil. Phosphor-containing material is deposited in the opening to form a coating on one or more light emitting surfaces of the chip. The opening may or may not substantially conform to a shape of the chip. The phosphor-containing material is cured with the stencil still in place. After curing, the stencil is removed from the substrate and the coated chip is separated from the substrate. The chip may then be subjected to further processing.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: December 6, 2016
    Assignee: Cree, Inc.
    Inventor: Peter S. Andrews
  • Microelectronic package having direct contact heat spreader and method of manufacturing same
    Patent number: 9508675
    Abstract: A method of fabricating a microelectronic package having a direct contact heat spreader, a package formed according to the method, a die-heat spreader combination formed according to the method, and a system incorporating the package. The method comprises metallizing a backside of a microelectronic die to form a heat spreader body directly contacting and fixed to the backside of the die thus yielding a die-heat spreader combination. The package includes the die-heat spreader combination and a substrate bonded to the die.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: November 29, 2016
    Assignee: Intel Corporation
    Inventors: Daoqiang Lu, Chuan Hu, Gilroy J. Vandentop, Shriram Ramanathan, Rajashree Baskaran, Valery M. Dubin
  • Electrostatic discharge protection apparatus and process
    Patent number: 9491840
    Abstract: In a process, at least one circuit element is formed in a substrate. A conductive layer is formed over the substrate and in electrical contact with the at least one circuit element. Electrostatic charges are discharged from the substrate via the conductive layer.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: November 8, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Chien Chang, Hsiang-Tai Lu, Dai-Jang Chen, Chih-Hsien Lin
  • N-polar III-nitride transistors
    Patent number: 9490324
    Abstract: An N-polar III-N transistor includes a III-N buffer layer, a first III-N barrier layer, and a III-N channel layer, the III-N channel layer having a gate region and a plurality of access regions on opposite sides of the gate region. The compositional difference between the first III-N barrier layer and the III-N channel layer causes a conductive channel to be induced in the access regions of the III-N channel layer. The transistor also includes a source, a gate, a drain, and a second III-N barrier layer between the gate and the III-N channel layer. The second III-N barrier layer has an N-face proximal to the gate and a group-III face opposite the N-face, and has a larger bandgap than the III-N channel layer. The lattice constant of the first III-N barrier layer is within 0.5% of the lattice constant of the buffer layer.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: November 8, 2016
    Assignee: Transphorm Inc.
    Inventors: Umesh Mishra, Srabanti Chowdhury, Carl Joseph Neufeld
  • Limiting adjustment of polishing rates during substrate polishing
    Patent number: 9490186
    Abstract: A method of controlling polishing includes polishing a region of a substrate at a first polishing rate, measuring a sequence characterizing values for the region of the substrate during polishing with an in-situ monitoring system, determining a polishing rate adjustment for each of a plurality of adjustment times prior to a polishing endpoint time, and adjusting a polishing parameter to polish the substrate at a second polishing rate. The time period is greater than a period between the adjustment times and the projected time is before the polishing endpoint time. The second polishing rate is the first polishing rate as adjusted by the polishing rate adjustment.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: November 8, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Dominic J. Benvegnu, Benjamin Cherian, Sivakumar Dhandapani, Harry Q. Lee
  • Integrated circuits having improved gate structures and methods for fabricating same
    Patent number: 9490129
    Abstract: Integrated circuits with improved gate structures and methods for fabricating integrated circuits with improved gate structures are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with fin structures. A gate-forming material is deposited over the semiconductor substrate and fin structures. The method includes performing a first etch process to etch the gate-forming material to form a gate line having a first side and a second side. The first side and second side of the gate line are bounded with material. The method includes performing a second etch process to etch a portion of the gate line bound by the material to separate the gate line into adjacent gate structures and to define a tip-to-tip distance between the adjacent gate structures.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: November 8, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Xiang Hu, Huang Liu
  • Semiconductor display device
    Patent number: 9478704
    Abstract: In the case where a still image is displayed on a pixel portion having a pixel, for example, a driver circuit for controlling writing of an image signal having image data to the pixel portion stops by stopping supply of power supply voltage to the driver circuit, and writing of an image signal to the pixel portion is stopped. After the driver circuit stops, supply of power supply voltage to a panel controller for controlling the operation of the driver circuit and an image memory for storing the image data is stopped, and supply of power supply voltage to a CPU for collectively controlling the operation of the panel controller, the image memory, and a power supply controller for controlling supply of power supply voltage to a variety of circuits in a semiconductor display device is stopped.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: October 25, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuji Nishijima, Seiichi Yoneda, Takuro Ohmaru, Jun Koyama
  • Flexible substrate member and light emitting device
    Patent number: 9478721
    Abstract: A flexible substrate member which can prevent breakage due to bending, regardless of a shape of a metal pattern, and a light emitting device which employs the flexible substrate. The flexible substrate member includes a plurality of metal wirings disposed on an insulating substrate which are spaced apart from each other via a groove portion. The groove portion includes an intersection region where a first groove portion and a second groove portion are intersected. The metal wirings includes a first metal wiring and a second metal wiring which are demarcated via the first groove portion in the intersection region, and a third metal wiring which is demarcated via the second groove portion with respect to the first metal wiring and the second metal wiring. The third metal wiring includes a projection which projects on an extension line of the first groove portion.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: October 25, 2016
    Assignee: NICHIA CORPORATION
    Inventor: Motokazu Yamada
  • Semiconductor device, printing apparatus, and manufacturing method thereof
    Patent number: 9472648
    Abstract: A manufacturing method of a semiconductor device including a DMOS transistor, an NMOS transistor and a PMOS transistor arranged on a semiconductor substrate, the DMOS transistor including a first impurity region and a second impurity region formed to be adjacent to each other, the first impurity region being of the same conductivity type as a drain region and a source region of the DMOS transistor, forming to enclose the drain region, and the second impurity region being of a conductivity type opposite to the first impurity region, forming to enclose the source region, the manufacturing method of the semiconductor device comprising forming the first impurity region and one of the NMOS transistor and the PMOS transistor, and forming the second impurity region and the other of the NMOS transistor and the PMOS transistor.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: October 18, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Nobuyuki Suzuki, Satoshi Suzuki, Masanobu Ohmura
  • Semiconductor device and method for manufacturing the same
    Patent number: 9472656
    Abstract: A semiconductor device including a minute transistor with a short channel length is provided. A gate insulating layer is formed over a gate electrode layer; an oxide semiconductor layer is formed over the gate insulating layer; a first conductive layer and a second conductive layer are formed over the oxide semiconductor layer; a conductive film is formed over the first conductive layer and the second conductive layer; a resist mask is formed over the conductive film by performing electron beam exposure; and then a third conductive layer and a fourth conductive layer are formed over and in contact with the first conductive layer and the second conductive layer, respectively, by selectively etching the conductive film.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: October 18, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Atsuo Isobe, Yoshinori Ieda, Masaharu Nagai
  • Flexible active matrix display
    Patent number: 9466651
    Abstract: High resolution active matrix structures are fabricated using techniques applicable to flexible substrates. A backplane layer including active semiconductor devices is formed using a semiconductor-on-insulator substrate. The substrate is thinned using a layer transfer technique or chemical/mechanical processing. Driver transistors are formed on the semiconductor layer of the substrate along with additional circuits that provide other functions such as computing or sensing. Contacts to passive devices such as organic light emitting diodes may be provided by heavily doped regions formed in the handle layer of the substrate and then isolated. A gate dielectric layer may be formed on the semiconductor layer, which functions as a channel layer, or the insulator layer of the substrate may be employed as a gate dielectric layer.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: October 11, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Stephen W. Bedell, III, Bahman Hekmatshoartabari, Ghavam G. Shahidi, Davood Shahrjerdi
  • Nanowire compatible E-fuse
    Patent number: 9466567
    Abstract: An e-fuse is provided in one area of a semiconductor substrate. The E-fuse includes a vertical stack of from, bottom to top, base metal semiconductor alloy portion, a first metal semiconductor alloy portion, a second metal semiconductor portion, a third metal semiconductor alloy portion and a fourth metal semiconductor alloy portion, wherein the first metal semiconductor alloy portion and the third metal semiconductor portion have outer edges that are vertically offset and do not extend beyond vertical edges of the second metal semiconductor alloy portion and the fourth metal semiconductor alloy portion.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: October 11, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Semiconductor device and method for manufacturing the same
    Patent number: 9466728
    Abstract: A highly reliable semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device is manufactured with a high yield, so that high productivity is achieved. In a semiconductor device including a transistor in which a source electrode layer and a drain electrode layer are provided over and in contact with an oxide semiconductor film, entry of impurities and formation of oxygen vacancies in an end face portion of the oxide semiconductor film are suppressed. This can prevent fluctuation in the electric characteristics of the transistor which is caused by formation of a parasitic channel in the end face portion of the oxide semiconductor film.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: October 11, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Motoki Nakashima, Masahiro Takahashi
  • Semiconductor device and method of fabricating same
    Patent number: 9466700
    Abstract: A lateral drain metal oxide semiconductor (LDMOS) device includes a well region having a second conductive type in a substrate, a body region having a first conductive type in the well region, a drift region having the second conductive type in the well region and spaced apart from the body region, a source region having the second conductive type in the body region, a drain region having the second conductive type in the drift region, a gate structure on the well region between the source region and the drain region, a shallow trench isolation (STI) structure in the drift region between the drain region and the source region, and a buried layer having the first conductive type in the well region under the drift region, a center of the buried layer being aligned with a center of the STI structure.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: October 11, 2016
    Assignee: Macronix International Co., Ltd.
    Inventors: Jiun-Yan Tsai, Shuo-Lun Tu, Shih-Chin Lien, Shyi-Yuan Wu
  • Metal-semiconductor contact structure with doped interlayer
    Patent number: 9466488
    Abstract: Disclosed herein is a method of forming a metal-to-semiconductor contact with a doped metal oxide interlayer. An insulating layer is formed on a top surface of a semiconductor substrate with target region at the top surface of the semiconductor substrate. An opening is etched through the insulating layer with the opening exposing a top surface of a portion of the target region. A doped metal oxide interlayer is formed in the opening and contacts the top surface of the target region. The remainder of the opening is filled with a metal plug, the doped metal oxide interlayer disposed between the metal plug and the substrate. The doped metal oxide interlayer is formed from one of tin oxide, titanium oxide or zinc oxide and is doped with fluorine.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: October 11, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou
  • Electronic devices with display-integrated light sensors
    Patent number: 9466653
    Abstract: An electronic device is provided, with a display and a display-integrated light sensor. The display includes a transparent cover layer, light-generating layers, and a touch-sensitive layer. The display-integrated light sensor is interposed between the transparent cover layer and a display layer such as the touch-sensitive layer or a thin-film transistor layer of the light-generating layers. The light-generating layers include a layer of organic light-emitting material. The display-integrated light sensor can be implemented as an ambient light sensor or a proximity sensor. The display-integrated light sensor may be a packaged light sensor that is integrated into the display layers of the display or may be formed from light-sensor components formed directly on a display circuitry layer such as the touch-sensitive layer or the thin-film transistor layer.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: October 11, 2016
    Assignee: Apple Inc.
    Inventors: Erik G. de Jong, Anna-Katrina Shedletsky, Prashanth S. Holenarsipur