Patents Examined by Anthony Ho
  • Patent number: 11817306
    Abstract: The present application provides a method for manufacturing a semiconductor package with air gaps for reducing capacitive coupling between conductive features. The method comprises: providing a first substrate with an integrated circuit; forming a first stack of insulating layers with first protruding portions on the integrated circuit; removing a topmost insulating layer in the first stack of insulating layers; forming through holes in the first stack to form a first semiconductor structure; providing a second substrate with an integrated circuit; forming a second stack of insulating layers with second protruding portions on the integrated circuit; forming a recess portion in the first stack to form a second semiconductor structure; and bonding the first semiconductor structure with the second semiconductor structure, with an air gap formed from the recess portion.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: November 14, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 11812625
    Abstract: A photoelectric converter includes a first electrode containing a transparent conductive material, a second electrode, and a multilayer body that is positioned between the first electrode and the second electrode, and that has a photoelectric conversion function. The multilayer body includes a first layer and a second layer positioned between the first layer and the second electrode. The first layer absorbs light in a first wavelength band of 360 nm or longer and transmits light in a second wavelength band, the second wavelength band including wavelengths longer than wavelengths included in the first wavelength band. The second layer absorbs the light in the second wavelength band. The multilayer body substantially does not have sensitivity for photoelectric conversion in the first wavelength band and has sensitivity for photoelectric conversion in the second wavelength band.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: November 7, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Katsuya Nozawa
  • Patent number: 11807616
    Abstract: The present application belongs to the field of organic materials, and relates to an organic compound, and an electronic element and an electronic device using same. The organic compound has a structure as represented by Formula I, and the organic compound can significantly improve the performance of an organic electroluminescent device when applied to the device.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: November 7, 2023
    Assignee: SHAANXI LIGHTE OPTOELECTRONICS MATERIAL CO., LTD.
    Inventors: Zhiyan Jia, Yun Liu, Youngkook Kim, Yingwen Li
  • Patent number: 11805665
    Abstract: A display panel, a manufacturing method thereof, and a mask plate group are provided. The display panel, from bottom to top, includes a light-sensing device, a substrate, and an anode layer. The anode layer in a display area includes a first light-transmitting layer and a reflective layer, which are stacked. The anode layer in a light-sensing area includes a second light-transmitting layer, and the light-sensing device is disposed in the light-sensing area.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: October 31, 2023
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Shuo Guo, Jing Wang
  • Patent number: 11804434
    Abstract: An integrated circuit apparatus and a power distribution network thereof are provided. The power distribution network includes a top wiring layer, a bottom wiring layer, and a first conductive path. The top wiring layer includes a first top trace and a second top trace extending along a first direction. The bottom wiring layer includes a first bottom trace extending along a second direction. The first bottom trace has an electric potential equal to that of the first top trace, but different from that of the second top trace. The first conductive path connected between the first top and bottom traces includes a first upper conductive structure and a first lower conductive structure that are located directly under the first top trace and the second top trace, respectively. A signal wire preselected region is defined between the first upper conductive structure and the first bottom trace.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: October 31, 2023
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chan-Wei Hsu, Chih-Wei Lin, Yun-Chih Chang
  • Patent number: 11800734
    Abstract: A light-emitting apparatus with low power consumption is provided. A light-emitting apparatus including a first light-emitting device and a first color conversion layer. The first light-emitting device includes an anode, a cathode, and an EL layer positioned between the anode and the cathode. The EL layer includes a layer including a material with a refractive index lower than or equal to 1.75 at 467 nm. The first color conversion layer includes a first substance capable of emission by absorbing light. Light emitted from the first light-emitting device enters the first color conversion layer.
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: October 24, 2023
    Inventors: Shunpei Yamazaki, Takeyoshi Watabe, Tomohiro Kubota, Airi Ueda, Satoshi Seo, Nobuharu Ohsawa, Yuko Kubota
  • Patent number: 11796520
    Abstract: A system and method for creating a scent database is described. An electronic sensing unit is used to receive an odorant sample and generate an electronic signature characterizing the sample received therein via a guiding unit that guides a first portion of the sample into an electronic sampling unit and a second portion of the sample towards an outlet. A control unit is used to receive data indicative of the signature generated by the sensing unit and data from user(s) indicative of olfactive descriptors characterizing the sample to which the users are exposed, enabling creation of a data record including first and second data corresponding to the same sample. The database includes data, each associated with a specific odorant sample, which may be used to characterise/formulate/create, a desired scent based on comparison of an electric signature generated for the scent and data records which signatures comply with best compliance criterion.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: October 24, 2023
    Inventor: Alon Daniel Gafsou
  • Patent number: 11798933
    Abstract: A semiconductor device includes first and second standard cells having respective semiconductor elements and first interconnection lines electrically connected to the semiconductor elements, on a substrate. A routing structure is provided, which is disposed on the first and second standard cells. The routing structure includes second interconnection lines electrically connected to the first interconnection lines. The first interconnection lines include a first power transmission line, which is configured to supply power to a semiconductor element, and a first signal transmission line electrically coupled to a semiconductor element.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: October 24, 2023
    Inventors: Jintae Kim, Jaeha Lee, Dongyeon Heo
  • Patent number: 11798958
    Abstract: The manufacturing method of the driving backplane includes following steps. A first flexible base is formed on a surface of a rigid substrate. At least one type of conductive pattern is formed on a surface of the first flexible base. At least one type of first via is provided in the rigid substrate. At least one type of second via is provided in the first flexible base by using the rigid substrate as a mask and a conductive pillar is formed in the at least one type of second via, so that the conductive pillars are connected to respective types of conductive pattern in one-to-one correspondence. At least one type of driving chip is correspondingly bonded to the conductive pillar formed in the at least one type of second via from a side of the first flexible base away from the at least one type of conductive pattern.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: October 24, 2023
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD
    Inventors: Wenqian Luo, Xiang Li, Zhanchang Bu
  • Patent number: 11800727
    Abstract: A perovskite solar cell includes following components provided successively from bottom to top: a transparent conductive glass substrate, a first transport layer, a perovskite layer, a second transport layer, a conductive electrode, and a back plate glass. The perovskite solar cell further includes an encapsulating adhesive. The transparent conductive glass substrate, the back plate glass, and the encapsulating adhesive form an enclosed space. The enclosed space contains a mixture of an inert gas and a methylamine gas, where a volume ratio of the inert gas to the methylamine gas is in a range from 9:1 to 5:5.
    Type: Grant
    Filed: June 12, 2023
    Date of Patent: October 24, 2023
    Assignee: CONTEMPORARY AMPEREX TECHNOLOGY CO., LIMITED
    Inventors: Bao Tu, Juanjuan Sun, Changsong Chen, Yongsheng Guo, Guodong Chen, Chuying Ouyang
  • Patent number: 11793007
    Abstract: A photoelectric conversion device includes a first electrode and a second electrode and a photoelectric conversion layer between the first electrode and the second electrode. The photoelectric conversion layer includes a first material and a second material, the first material and the second material being configured to form a pn junction, and a third material different from the first material and the second material. The third material includes an electron withdrawing group.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: October 17, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jisoo Shin, Kyung Bae Park, Sung Jun Park, Jeong Il Park, Seon-Jeong Lim, Youn Hee Lim, Yeong Suk Choi, Taejin Choi
  • Patent number: 11793006
    Abstract: Disclosed are a memristor device, a method of fabricating the same, a synaptic device including a memristor device, and a neuromorphic device including a synaptic device. The disclosed memristor device may comprise a first electrode, a second electrode disposed to be spaced apart from the first electrode; and a resistance changing layer including a copolymer between the first electrode and the second electrode. The copolymer may be a copolymer of a first monomer and a second monomer, and the first polymer formed from the first monomer may have a property that diffusion of metal ions is faster than that of the second polymer formed from the second monomer. The second polymer may have a lower diffusivity of metal ions as compared with the first polymer. The first monomer may include vinylimidazole (VI). The second monomer may include 1,3,5-trivinyl-1,3,5-trimethylcyclotrisiloxane (V3D3). The copolymer may include p(V3D3-co-VI).
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: October 17, 2023
    Assignees: SK hynix Inc., Korea Advanced Institute of Science and Technology
    Inventors: Sangsu Park, Sung-Yool Choi, Sung Gap Im, Sang Yoon Yang, Jungyeop Oh
  • Patent number: 11793031
    Abstract: A display device includes pixels. Each of the pixels includes: a first transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor including a gate electrode connected to a first scan line, a first electrode connected to a data line, and a second electrode connected to the second node; a first sub-transistor including a gate electrode connected to the first scan line, a first electrode connected to the first node, and a second electrode connected to a fourth node; and a second sub-transistor including a gate electrode connected to the first scan line, a first electrode connected to the fourth node, and a second electrode connected to the third node. A channel width of the second sub-transistor is wider than a channel width of the first sub-transistor.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: October 17, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young In Hwang, Ji Hye Kong, Suk Hoon Ku, Sung Wook Kim, Jin A Lee, Yun Sik Joo
  • Patent number: 11793085
    Abstract: According to an aspect, there is provided a method of forming a magnetic tunneling junction (MTJ) device, including: forming a layer stack including an MTJ layer structure and a spin-orbit torque (SOT) layer below the MTJ layer structure; forming a first etch mask over the layer stack, the first etch mask including a first mask line extending in a first horizontal direction; patterning the layer stack to form an MTJ line extending in the first horizontal direction, the patterning including etching while the first etch mask masks the layer stack, and stopping etching on or above the SOT-layer; forming sidewall spacers on one or both sides of the MTJ line; while the sidewall spacers mask the SOT-layer, etching the SOT-layer to form a patterned layer stack including the MTJ line and a first patterned SOT-layer; forming a second etch mask over the patterned layer stack, the second etch mask including a second mask line extending in a second horizontal direction across the MTJ line; and patterning the patterned la
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: October 17, 2023
    Assignee: IMEC vZw
    Inventors: Davide Francesco Crotti, Kevin Garello
  • Patent number: 11793015
    Abstract: Embodiments of the disclosed subject matter provide a device including one or more organic layers that include an emissive layer, a first electrode layer disposed over the one or more organic layers, a plurality of nanostructures formed as part of the first electrode layer, a substrate, a second electrode layer, where the second electrode layer is disposed on the substrate, the one or more organic layers are disposed on the second electrode layer, and the first electrode layer including the plurality of nanostructures is disposed on the one or more organic layers and within the predetermined threshold distance of the emissive layer.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: October 17, 2023
    Assignee: Universal Display Corporation
    Inventors: Vinod M. Menon, Michael Fusella, Nicholas J. Thompson
  • Patent number: 11793008
    Abstract: An imaging device includes: pixels arranged one-dimensionally or two-dimensionally, each of the pixels including an electrode that is electrically connected to the other pixels, a charge capturing unit that is separated from the other pixels, and a photoelectric conversion layer that is located between the electrode and the charge capturing unit, the photoelectric conversion layer being continuous among the pixels. The photoelectric conversion layer contains semiconductor carbon nanotubes, and one of a first substance and a second substance, the first substance having an electron affinity larger than that of the semiconducting carbon nanotubes, the second substance having a ionization energy smaller than that of the semiconductor carbon nanotubes.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: October 17, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Katsuya Nozawa
  • Patent number: 11785810
    Abstract: A display substrate, a manufacturing method thereof, and a display device. The method includes: forming a pixel definition layer transitional pattern on a base substrate, the pixel definition layer transitional pattern being provided at a lateral surface with an undercut; forming a common layer, which is broken at the undercut, on the base substrate; removing the undercut to obtain a pattern of a pixel definition layer; and forming a cathode on the base substrate.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: October 10, 2023
    Assignees: HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Kui Gong, Xianxue Duan
  • Patent number: 11784241
    Abstract: Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: October 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Chiang, Ching-Wei Tsai, Chi-Wen Liu, Ying-Keung Leung
  • Patent number: 11784150
    Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: October 10, 2023
    Assignee: Intel Corporation
    Inventors: Dae-Woo Kim, Ajay Jain, Neha M. Patel, Rodrick J. Hendricks, Sujit Sharan
  • Patent number: 11778843
    Abstract: A light-emitting element includes an anode, a hole transport layer, a quantum dot light-emitting layer, an electron transport layer, and a cathode, in this order. The electron transport layer includes a particulate metal oxide and a conductive resin that disperses the metal oxide.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: October 3, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hisayuki Utsumi, Youhei Nakanishi, Masayuki Kanehiro, Shota Okamoto, Hiroki Imabayashi, Tatsuya Ryohwa, Kanako Nakata