Patents Examined by Anthony Ho
  • Patent number: 11887890
    Abstract: Partial self-aligned contact structures are provided. In one aspect, a method of forming a semiconductor device includes: patterning fins in a substrate; forming a gate(s) over the fins, separated from source/drains by first spacers, wherein a lower portion of the gate(s) includes a workfunction-setting metal, and an upper portion of the gate(s) includes a core metal between a metal liner; recessing the metal liner to form divots in the upper portion of the gate(s) in between the first spacers and the core metal; forming second spacers in the divots such that the first spacers and the second spacers surround the core metal in the upper portion of the gate(s); forming lower source/drain contacts in between the first spacers over the source/drains; recessing the lower source/drain contacts to form gaps over the lower source/drain contacts; and forming source/drain caps in the gaps. A semiconductor device is also provided.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: January 30, 2024
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Veeraraghavan Basker, Alexander Reznicek, Junli Wang
  • Patent number: 11881477
    Abstract: An array of poly lines on an active device area of an integrated chip is extended to form a dummy device structure on an adjacent isolation region. The resulting dummy device structure is an array of poly lines having the same line width, line spacing, and pitch as the array of poly lines on the active device area. The poly lines of the dummy device structure are on grid with the poly lines on the active device area. Because the dummy device structure is formed of poly lines that are on grid with the poly lines on the active device area, the dummy device structure may be much closer to the active device area than would otherwise be possible. The resulting proximity of the dummy device structure to the active device area improves anti-dishing performance and reduces empty space on the integrated chip.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: January 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung Feng Chang, Bao-Ru Young, Yu-Jung Chang, Tzung-Chi Lee, Tung-Heng Hsieh, Chun-Chia Hsu
  • Patent number: 11877508
    Abstract: Provided are a fluorinated compound for patterning a metal or an electrode (cathode), an organic electronic element using the same, and an electronic device thereof, wherein a fine pattern of the electrode is formed by using the fluorinated compound as a material for patterning a metal or an electrode (cathode), without using a shadow mask, and it is possible to more easily apply UDC since it is easy to manufacture a transparent display having high light transmittance.
    Type: Grant
    Filed: February 15, 2023
    Date of Patent: January 16, 2024
    Assignees: DUK SAN NEOLUX CO., LTD., SAMSUNG DISPLAY CO., LTD.
    Inventors: Ki Won Kim, Kyung Hwan Oh, Bu Yong Yun, Hyung Dong Lee, Jin Woo Shin, Soung Yun Mun, Jae Duk Yoo, Jung Geun Lee, Joon Gu Lee, Yeon Hwa Lee, Mi Kyung Kim, Ji Hyun Seo, Kwan Hee Lee
  • Patent number: 11871600
    Abstract: A display device with high display quality is provided. The display device includes a first lower electrode, a first EL layer over the first lower electrode, a second lower electrode, a second EL layer over the second lower electrode, an upper electrode over the first EL layer and the second EL layer, a first region not provided with the first lower electrode below the first EL layer, and a second region not provided with the second lower electrode below the second EL layer. In the first region, the upper electrode is positioned not to be in contact with the first lower electrode. In the second region, the upper electrode is positioned not to be in contact with the second lower electrode.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: January 9, 2024
    Inventors: Kenichi Okazaki, Shingo Eguchi, Hiroki Adachi
  • Patent number: 11871594
    Abstract: An electroluminescent device and a display device including the electroluminescent device. The electroluminescent device includes a first electrode and a second electrode each having a surface opposite the other; a light emitting layer disposed between the first electrode and the second electrode, the light emitting layer including quantum dots; and an electron transport layer disposed between the light emitting layer and the second electrode, the electron transport layer including inorganic material nanoparticles including an anion dopant including P, N, C, Cl, F, Br, S, or a combination thereof.
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: January 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung woo Kim, Moon Gyu Han, Eun joo Jang, Kun su Park
  • Patent number: 11871654
    Abstract: The present invention relates to heteroleptic complexes comprising a phenylimidazole or phenyltriazole unit bonded via a carbene bond to a central metal atom, and phenylimidazole ligands attached via a nitrogen-metal bond to the central atom, to OLEDs which comprise such heteroleptic complexes, to light-emitting layers comprising at least one such heteroleptic complex, to a device selected from the group consisting of illuminating elements, stationary visual display units and mobile visual display units comprising such an OLED, to the use of such a heteroleptic complex in OLEDs, for example as emitter, matrix material, charge transport material and/or charge blocker.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: January 9, 2024
    Assignee: UDC IRELAND LIMITED
    Inventors: Evelyn Fuchs, Oliver Molt, Korinna Dormann, Thomas Gessner, Nicolle Langer, Ingo Muenster, JianQiang Qu, Christian Lennartz, Christian Schildknecht, Soichi Watanabe, Gerhard Wagenblast, Guenter Schmid, Herbert Friedrich Boerner, Volker van Elsbergen
  • Patent number: 11871625
    Abstract: Provided are a display substrate and a preparation method thereof, and a display apparatus. The display substrate includes a silicon-based substrate and an array structure layer arranged on the silicon-based substrate; a driving transistor and a first power line being arranged in the silicon-based substrate in the display area, a light emitting element being disposed on the array structure layer in the display area, a first electrode of the driving transistor being connected with the first power line, and a second electrode of the driving transistor being connected with an anode of the light emitting element; a power supply electrode and a second power line being arranged in the silicon-based substrate in the peripheral area, the power supply electrode being connected with the second power line.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: January 9, 2024
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Pengcheng Lu, Shengji Yang, Kuanta Huang, Xiaochuan Chen, Yage Song, Yanming Wang, Hui Wang, Dongdong Duan, Jiantong Li, Xiao Bai, Yunlong Li, Shuai Tian, Zhijian Zhu, Yu Ao, Junbo Wei, Chao Pu, Yuanlan Tian
  • Patent number: 11862704
    Abstract: Provided are electronic devices and methods of manufacturing the same. An electronic device may include a substrate, a gate electrode on the substrate, a ferroelectric layer between the substrate and the gate electrode, and a carbon layer between the substrate and the ferroelectric layer. The carbon layer may have an sp2 bonding structure.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: January 2, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinseong Heo, Yunseong Lee, Sanghyun Jo, Keunwook Shin, Hyeonjin Shin
  • Patent number: 11864460
    Abstract: An organic light emitting device including a first electrode, a second electrode provided opposite to the first electrode, and an organic material layer provided between the first electrode and the second electrode, wherein the organic material layer includes a hole transfer layer and an electron blocking layer, and the hole transfer layer and the electron blocking layer include a compound of Chemical Formula 1, the materials of the hole transfer layer and the electron blocking layer are different from each other, and one or more layers that are not the hole transfer layer and the electron blocking layer of the organic material layer include a compound of Chemical Formula 2.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: January 2, 2024
    Assignee: LG CHEM, LTD.
    Inventors: Sang Duk Suh, Jae Seung Ha, Dong Hoon Lee, Minseung Chun, Ji Young Choi, Woochul Lee, Joo Ho Kim, Hoon Jun Kim
  • Patent number: 11849602
    Abstract: An organic light emitting display device may include a filling part filling a space between a second substrate and an organic light emitting diode, and a dam structure disposed in a non-display area and surrounding the filling part. At least one of the dam structure and the filling part includes a getter. The getter of the present disclosure is composed of magnesium oxide particles whose surfaces are modified into a first surface modification part made of an amino silane-based compound and a second surface modification part bound to the first surface modification part and made of a compound containing an acrylate group and a methacrylate group. Accordingly, it is possible to provide an organic light emitting display device that has high transparency and of which optical properties and durability are improved by minimizing permeation of water and oxygen.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: December 19, 2023
    Assignees: LG Display Co., Ltd., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Jaebin Song, Dawoon Jeong, SungHee Kim, Suyeon Lee, JaeMin Myoung, Sung-Doo Baek, MinSeong Kim
  • Patent number: 11845824
    Abstract: The present disclosure provides a novel polymer compound prepared by curing a compound represented by the following Chemical Formula 1 and a compound represented by the following Chemical Formula 4, and an organic light emitting device comprising the same: with each variable being defined therein.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: December 19, 2023
    Inventors: Minho Hwang, Ho Gyu Lee, Jaechol Lee
  • Patent number: 11844227
    Abstract: A thin film transistor and manufacturing method thereof, an electronic device are provided, which includes: a gate electrode, a gate insulation layer, an active layer, a first electrode and a second electrode are on a base substrate, the active layer made of a one-dimensional semiconductor nano material includes a first electrode region, a second electrode region, a first channel region, a second channel region; the first electrode region and the second electrode region are in contact with the first electrode and the second electrode respectively, the first channel region is directly connected with the first channel region and the second channel region respectively, the second channel region is a first doped region and between the first electrode region and the second electrode region; an energy level of the second channel region is different from that of the first channel region corresponding to the energy level of the second channel region.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: December 12, 2023
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., PEKING UNIVERSITY
    Inventors: Qi Huang, Xuelei Liang, Hu Meng
  • Patent number: 11839145
    Abstract: An organic light emitting diode includes a first electrode, a hole transport region disposed on the first electrode, an emission layer disposed on the hole transport region, an electron transport region disposed on the emission layer, and a second electrode disposed on the electron transport region. The hole transport region includes a first hole transport layer which is directly disposed on the lower portion of the emission layer and has a first refractive index, and a second hole transport layer which is disposed on the lower portion of the first hole transport layer and has a second refractive index, thereby exhibiting an improved luminous efficiency characteristic.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: December 5, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jimyoung Ye, Hyomin Ko
  • Patent number: 11832458
    Abstract: A carbon nanotube field effect transistor (CNFET), that has a channel formed of carbon nanotubes (CNTs), includes a layered deposit of a nonstoichiometric doping oxide (NDO), such as HfOX, where the concentration of the NDO varies through the thickness of the layer(s). An n-type metal-oxide semiconductor (NMOS) CNFET made in this manner can achieve similar ON-current, OFF-current, and/or threshold voltage magnitudes to a corresponding p-type metal-oxide semiconductor (PMOS) CNFET. Such an NMOS and PMOS can be used to achieve a symmetric complementary metal-oxide semiconductor (CMOS) CNFET design.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: November 28, 2023
    Assignee: Massachusetts Institute of Technology
    Inventors: Christian Lau, Max Shulaker
  • Patent number: 11829072
    Abstract: Embodiments related to emissive display device structures having an emissive display element and a metamaterial lens having a plurality of nanoparticles over an emissive surface of the emissive display element to control the angular distribution of light emitted from the emissive display element, displays having such controlled emissive display device structures, systems incorporating such controlled emissive display device structures, and methods for fabricating them are discussed.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: November 28, 2023
    Assignee: Intel Corporation
    Inventors: Khaled Ahmed, Richmond Hicks
  • Patent number: 11832466
    Abstract: An electroluminescent element according to an aspect of the disclosure includes: a pair of a cathode electrode and an anode electrode; a light-emitting layer provided between the cathode electrode and the anode electrode; an electron transport layer provided between the cathode electrode and the light-emitting layer; and a hole transport layer provided between the anode electrode and the light-emitting layer. The light-emitting layer includes ZnSe-based quantum dots including ZnSe and one of the electron transport layer and the hole transport layer is composed of ZnO particles having an average particle size of 3 nm or greater and 30 nm or less.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: November 28, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tadashi Kobashi, Kenichi Yoshimura, Masashi Kago, Noboru Iwata
  • Patent number: 11829183
    Abstract: Various configurations and arrangements for touchscreens are disclosed to accommodate for one or more optical discontinuities that can be present within these touchscreens. When the one or more optical discontinuities are present, these configurations and arrangements of the touchscreens present a single layer of transparent conductive material that can be difficult to perceive by a human eye when viewing the touchscreens. Additionally, various edge correction techniques are disclosed to adjust mutual capacitances along a perimeter of the touchscreens. These edge correction techniques adjust mutual capacitances such that the values of the mutual capacitances are substantially uniform throughout.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: November 28, 2023
    Assignee: ELO TOUCH SOLUTIONS, INC.
    Inventors: Gazi Ali, Khalid Azim, Joel Kent
  • Patent number: 11823877
    Abstract: According to one embodiment of the present disclosure, there is provided a substrate processing system for processing a plurality of substrates including: a processor configured to perform a process on the substrate; a transport device configured to repeatedly transport the plurality of substrates with respect to the processor; and a controller configured to control the process of the substrate in the processor, wherein the controller is configured to: execute the process based on a process recipe, which is a control program for executing the process; and set an offset time, which is a function corresponding to a number of the substrates processed by the processor or a function corresponding to a parameter equivalent to the number of the processed substrates, with respect to a step time for a step of the process recipe.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: November 21, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Koichi Miyashita, Makoto Horikawa, Satoshi Gomi
  • Patent number: 11824150
    Abstract: A display device comprising: a substrate having a first surface and a second surface opposite to the first surface; a plurality of pixels arrayed in a display region of the substrate; an inorganic light-emitting element provided to each of the pixels on the first surface of the substrate; cathode wiring provided in a peripheral region between the display region and an end of the substrate on the first surface of the substrate and electrically coupled to the inorganic light-emitting element; and a heat radiator provided on the second surface of the substrate, wherein the substrate has a through hole that connects the first surface with the second surface in the peripheral region of the substrate and overlaps the cathode wiring in planar view viewed from a direction perpendicular to the first surface of the substrate.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: November 21, 2023
    Assignee: Japan Display Inc.
    Inventors: Masanobu Ikeda, Yasuhiro Kanaya
  • Patent number: 11821937
    Abstract: The embodiments of the present disclosure provide a semiconductor base plate and a test method thereof. When a first test line and a second test line in the semiconductor base plate are tested, a resistivity of the first test line can be tested by directly loading voltages to a first test pad and a second test pad after a first conductive layer is formed and before a first insulating layer is formed. After a second conductive layer is formed, a resistivity of the second test line is tested by loading voltages to a third test pad and a fourth test pad.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: November 21, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Qiang Li