Abstract: Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.

Abstract: The present disclosure relates a display device, including a flexible display panel with a bendable region and a flexible support attached to a back side of the flexible display panel, the flexible support includes a flexible support body, and a first part of the flexible support body corresponding to the bendable region is provided with a concave structure.

Abstract: The present disclosure provides a light emitting diode, a method of preparing the same, and a display device. The light emitting diode includes an anode, a quantum dot light emitting layer, an electron transport layer, a cathode, and a transition layer located between the electron transport layer and the cathode, the cathode including a transparent conductive oxide material, and a material of the transition layer having a work function WF between an LUMO of a material of the electron transport layer and a work function WF of a material of the cathode.

Abstract: A method for preparing a perovskite solar cell is disclosed, which comprises the following steps: providing a first electrode; forming an active layer on the first electrode; and forming a second electrode on the active layer. Herein, the active layer can be prepared by the following steps: mixing a perovskite precursor and a solvent mixture to form a precursor solution, wherein the solvent mixture comprises a first solvent and a second solvent, the first solvent is selected from the group consisting of ?-butyrolactone (GBL), dimethyl sulfoxide (DMSO), 2-methylpyrazine (2-MP), dimethylformamide (DMF), 1-methyl-2-pyrrolidone (NMP), dimethylacetamide (DMAc) and a combination thereof, and the second solvent is an alcohol; and coating the first electrode with the precursor solution and heating the precursor solution to form the active layer.

Abstract: A method includes providing a structure including a carrier wafer, and a first device wafer with an adhesion layer between the carrier wafer and the first device wafer; and forming a plurality of first ablation structures in the structure, each of the plurality of first ablation structures extending through the first device wafer, the adhesion layer and a portion of the carrier wafer. Each of the plurality of first ablation structures has a portion inside the carrier wafer with a depth no greater than one half of a thickness of the carrier wafer. The first device wafer includes a plurality of first dies, each pair of adjacent first dies being separated by one of the plurality of first ablation structures. The plurality of first ablation structures are formed by either laser grooving or mechanical sawing.

Abstract: A field-effect transistor comprises, on a substrate, a source electrode, a drain electrode, and a gate electrode; a semiconductor layer in contact with the source electrode and the drain electrode; wires individually electrically connected to the source electrode and the drain electrode; and a gate insulating layer that insulates the semiconductor layer from the gate electrode, wherein a connecting portion between the source electrode and the wire forms a continuous phase, and a connecting portion between the drain electrode and the wire forms a continuous phase, the portions constituting the continuous phases contain at least an electrically conductive component and an organic component, and integrated values of optical reflectance at a region of a wavelength of 600 nm or more and 900 nm or less on the wires are higher than integrated values of optical reflectance at a region of a wavelength of 600 nm or more and 900 nm or less on the source electrode and the drain electrode.

Abstract: Embodiments of the present invention relate to an organic electronic device capable of ensuring high luminous efficiency, low driving voltage and high heat resistance, and improving color purity or lifespan.

Abstract: A MOS transistor, in particular a vertical channel transistor, includes a semiconductor body housing a body region, a source region, a drain electrode and gate electrodes. The gate electrodes extend in corresponding recesses which are symmetrical with respect to an axis of symmetry of the semiconductor body. The transistor also has spacers which are also symmetrical with respect to the axis of symmetry. A source electrode extends in electrical contact with the source region at a surface portion of the semiconductor body surrounded by the spacers and is in particular adjacent to the spacers. During manufacture the spacers are used to form in an auto-aligning way the source electrode which is symmetrical with respect to the axis of symmetry and equidistant from the gate electrodes.

Abstract: An organic light-emitting device includes: a first electrode; a second electrode facing the first electrode; m emission units stacked between the first electrode and the second electrode, each emission unit including at least one emission layer; and m?1 charge generating layers respectively located between two adjacent emission units among them emission units, each of the charge generating layers including one n-type charge generating region and one p-type charge generating region, wherein m is an integer of 2 or more, and at least one of the m?1 p-type charge generating regions includes a phosphate-containing compound.

Abstract: Photoelectric conversion element including: substrate; first electrode; hole-blocking layer; photoelectric conversion layer; and second electrode, the photoelectric conversion layer including electron-transporting layer and hole-transporting layer, wherein in photoelectric conversion element edge part in direction orthogonal to stacking direction of the substrate, first electrode, hole-blocking layer, photoelectric conversion layer, and second electrode, electron-transporting layer outermost end is positioned inside than first electrode outermost end, hole-transporting layer outermost end is positioned outside than second electrode outermost end, and the second electrode outermost end is positioned inside than the electron-transporting layer outermost end, and height of edge part including the first electrode outermost end in the stacking direction is smaller than total of average thicknesses of first electrode, hole-blocking layer, and electron-transporting layer, where the height is distance between substra

Abstract: A semiconductor device includes: a substrate; a test transistor over the substrate; and multi-level metal interconnections formed over the substrate spaced apart from the test transistor, wherein at least one metal interconnection among the multi-level metal interconnections is a spiral metal interconnection.

Abstract: A semiconductor package is provided, including a package component and a number of conductive features. The package component has a non-planar surface. The conductive features are formed on the non-planar surface of the package component. The conductive features include a first conductive feature and a second conductive feature respectively arranged in a first position and a second position of the non-planar surface. The height of the first position is less than the height of the second position, and the size of the first conductive feature is smaller than the size of the second conductive feature.

Abstract: A method for enhancing aggregation state stability of organic semiconductor (OSC) films includes constructing the OSC film; introducing uniform and discontinuous nanoparticles on a surface of the film or an inside of the film. Electrical properties of the OSC film are not influenced by introducing the nanoparticles. Grain boundary, dislocation, stacking fault, and surface of the film are pinned by the nanoparticles, increasing potential barrier of the aggregation state evolution of the film, and thus enhancing the stability of the aggregation state and greatly improving maximum working temperature and storage lifetime of organic field-effect transistors. Under room temperature storage, morphology of the OSC film introduced with the nanoparticles is difficult to change, so that the stability of electrical properties of organic transistor components prepared from the film is ensured in a high-temperature and atmospheric working environment.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a package substrate, a first die over the package substrate, the first die having a first bump pitch, a second die over the package substrate, the second die having a second bump pitch that is greater than the first bump pitch, and a plurality of conductive traces over the package substrate, the plurality of conductive traces electrically coupling the first die to the second die. In an embodiment, a first end region of the plurality of conductive traces proximate to the first die has a first line space (L/S) dimension, and a second end region of the plurality of conductive traces proximate to the second die has a second L/S dimension. In an embodiment, the second L/S dimension is greater than the first L/S dimension.

Abstract: The present application relates to a nitrogen-containing compound. The structural formula of the nitrogen-containing compound is as shown in a Formula 1, in which a ring A and a ring B are each independently selected from a benzene ring or a fused aromatic ring with 10 to 14 ring-forming carbon atoms, and at least one of the ring A and the ring B is selected from the fused aromatic ring with 10 to 14 ring-forming carbon atoms; L is selected from a single bond, a substituted or unsubstituted arylene group with 6 to 30 carbon atoms, and a substituted or unsubstituted heteroarylene group with 3 to 30 carbon atoms; and Het is a substituted or unsubstituted nitrogen-containing heteroaryl group with 3 to 30 carbon atoms. The nitrogen-containing compound of the present application can improve the luminous efficiency of an organic electroluminescent device and the conversion efficiency of a photoelectric conversion device using the nitrogen-containing compound.

Abstract: A method of p-type doping a carbon nanotube includes the following steps: providing a single carbon nanotube; providing a layered structure, wherein the layered structure is a tungsten diselenide film or a black phosphorus film; and p-type doping at least one portion of the carbon nanotube by covering the carbon nanotube with the layered structure.

Abstract: The present invention relates to a process for the preparation of a top-gate, bottom-contact organic field effect transistor on a substrate, which organic field effect transistor comprises source and drain electrodes, a semiconducting layer, a cured first dielectric layer and a gate electrode, and which process comprises the steps of: i) applying a composition comprising an organic semiconducting material to form the semiconducting layer, ii) applying a composition comprising a first dielectric material and a crosslinking agent carrying at least two azide groups to form a first dielectric layer, iii) curing portions of the first dielectric layer by light treatment, iv) removing the uncured portions of the first dielectric layer, and v) removing the portions of the semiconducting layer that are not covered by the cured first dielectric layer, wherein the first dielectric material comprises a star-shaped polymer consisting of at least one polymer block A and at least two polymer blocks B, wherein each polymer b

Abstract: An electroluminescent device, a manufacturing method thereof, and a display apparatus are provided. The electroluminescent device includes an anode layer, a light emitting layer, a cathode layer, a hole transport layer located between the anode layer and the light emitting layer, and a electron transport layer located between the cathode layer and the light emitting layer. The electroluminescent device further includes: a first interface modification layer between the light emitting layer and one of the hole transport layer and the electron transport layer; wherein an energy level of the first interface modification layer matches an energy level of the light emitting layer and an energy level of the one of the hole transport layer and the electron transport layer.

Abstract: Provided are a light emitting device includes a first electrode and a second electrode facing each other; an emissive layer disposed between the first electrode and the second electrode and a display device including the same. The emissive layer comprises: a first emission layer disposed on the first electrode and having a hole transporting property; a second emission layer and a third emission layer disposed on the first emission layer; wherein the second emission layer comprises an organic compound having a bipolar transport property and the third emission layer has a composition different from the first emission layer and the second emission layer; wherein the first emission layer, the second emission layer, and the third emission layer comprises a plurality of quantum dots, and wherein the first emission layer, the second emission layer, and the third emission layer are configured to emit light of a same color.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a logic circuit provided on the substrate, and a memory cell array provided over the logic circuit that includes a plurality of electrode layers stacked on top of one another and a semiconductor layer provided over the plurality of electrode layers. The semiconductor device further includes a first plug and a second plug provided above the logic circuit and electrically connected to the logic circuit, a bonding pad provided on the first plug, and a metallic wiring layer provided on the memory cell array, electrically connected to the semiconductor layer, and electrically connected to the second plug.