Abstract: Disclosed are a photoelectric conversion device and an organic sensor and an electronic device including the same. The photoelectric conversion device includes a first and a second electrode, a photoelectric conversion layer between the first and the second electrode and configured to absorb light in at least one portion of a wavelength spectrum and to convert the absorbed light into an electric signal, and a buffer layer between the second electrode and the photoelectric conversion layer and including a mixture of at least two materials. The mixture includes a first and a second material. The first material has an energy bandgap of at least about 3.2 eV and a HOMO energy level of at least about 6.0 eV. The second material has an energy bandgap of less than or equal to about 2.8 eV and a HOMO energy level of at least about 6.0 eV.

Abstract: Methods of forming films of aligned carbon nanotubes on a substrate surface are provided. The films are deposited from carbon nanotubes that have been concentrated and confined at a two-dimensional liquid/liquid interface. The liquid/liquid interface is formed by a dispersion of organic material-coated carbon nanotubes that flows over the surface of an immiscible liquid within a flow channel. Within the interface, the carbon nanotubes self-organize via liquid crystal phenomena and globally align along the liquid flow direction. By translating the interface across the substrate, large-area, wafer-scale films of aligned carbon nanotubes can be deposited on the surface of the substrate in a continuous and scalable process.

Abstract: A light-emitting structure includes a substrate, a sub-pixel stack, a cover layer over the sub-pixel stack, and at least one interface between the substrate and the cover layer. The at least one interface has an interface roughness. The sub-pixel stack includes an emissive layer between a first transport layer and a second transport layer, a first electrode layer coupled to the first transport layer, and a second electrode layer coupled to the second transport layer. The sub-pixel stack is over the substrate and configured to emit light including a scattering component caused by the interface roughness and a cavity component separate from the scattering component. A ratio of a luminance of the scattering component to a luminance of the cavity component increases with a viewing angle relative to a display normal. An optical power of the scattering component is a fraction of an optical power of the cavity component.

Abstract: A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.

Abstract: A die can be applied to a front conductive layer. Openings can be formed in the conductive layer over contact points on the die. The openings can be filled with a conductive material to electrically couple the conductive layer to the contact points on the die. The front conductive layer can be etched to form a first conductive pattern. Conductive standoffs can be formed on portions of the front conductive layer. An additional front conductive layer can be laminated onto the front side. Openings can be formed in the additional front conductive layer over the standoffs. The openings can be filled with a conductive material to electrically couple the additional conductive layer to the underlying standoffs. The additional conductive layer can be etched to form a second conductive pattern.

Abstract: A thermally activated delayed fluorescent molecular material, a method for synthesizing the same, and an organic electroluminescent device are provided. The thermally activated delayed fluorescent molecular material includes an electron donor and an electron acceptor containing an indenyl group. A phenyl group in diphenylamine or triphenylamine in a donor molecule is replaced with an indenyl group, so that the electron-donating ability of the donor is increased, and the non-radiative transition rate is effectively suppressed, thereby increasing the photoluminescence quantum yield (PLQY) of the molecule. Further, the torsion angle between the electron donor and the electron acceptor is also increased, while the electron cloud overlap between the highest occupied molecular orbital (HOMO) and the lowest unoccupied molecular orbital (LUMO) is reduced, thereby obtaining a smaller ?EST value.

Abstract: A compound represented by formula (1): wherein Ar1 and Ar2 each represents a group represented by formula (3); and R1 represents a naphthylphenyl group, a biphenylyl group, a terphenylyl group, a biphenylenyl group, a naphthyl group, or a phenylnaphthyl group; R2 represents a hydrogen atom; R5 and R6 are as defined in the description is provided. An electroluminescence device which contains the compound of formula (1) is also provided.

Abstract: An integrated circuit (IC) includes a semiconductor surface layer of a substrate including circuitry formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal (MIM) capacitor. A multi-layer metal stack on the semiconductor surface layer includes a bottom plate contact metal layer including a bottom capacitor plate contact. A first interlevel dielectric (ILD) layer is over the bottom plate contact metal layer. The MIM capacitor includes a trench in the first ILD layer over the bottom capacitor plate contact, wherein the trench is lined by a bottom capacitor plate with a capacitor dielectric layer thereon, and a top capacitor plate on the capacitor dielectric layer. A fill material fills the trench to form a filled trench. A second ILD layer is over the filled trench. A filled via through the second ILD layer provides a connection to the top capacitor plate.

Abstract: In some embodiments, the present disclosure relates to a method that includes forming an isolation structure over a reflector electrode and forming a protective layer over the isolation structure. Further, a first removal process is performed to form a first opening in the protective layer and the isolation structure to expose a first surface of the reflector electrode. A cleaning process is performed to clean the first surface of the reflector electrode. A conductive layer is formed over the protective layer and within the first opening. The conductive layer includes a different material than the protective layer. A second removal process is performed to remove peripheral portions of the protective layer and the conductive layer to form a via structure within the opening, extending through the isolation structure to contact the reflector electrode, and including the protective layer and the conductive layer.

Abstract: Generally, the present disclosure provides example embodiments relating to a package that may be attached to a printed circuit board (PCB). In an embodiment, a structure includes a package. The package includes one or more dies and metal pads on an exterior surface of the package. At least some of the metal pads are first solder ball pads. The structure further includes pins, and each of the pins is attached to a respective one of the metal pads.

Abstract: A quantum dot device including a first electrode and a second electrode each having a surface opposite the other, a quantum dot layer disposed between the first electrode and the second electrode, and an electron auxiliary layer disposed between the quantum dot layer and the second electrode, wherein the electron auxiliary layer includes inorganic nanoparticles including an alkaline-earth metal, and an alkali metal, an alkali metal compound, or a combination thereof, and an electronic device including the quantum dot device.

Abstract: A semiconductor device includes a substrate, a fin protruding from the substrate, and a gate stack over the substrate and engaging the fin. The fin having a first end and a second end. The semiconductor device also includes a dielectric layer abutting the first end of the fin and spacer features disposed on sidewalls of the gate stack and on a top surface of the dielectric layer.

Abstract: In some examples, a package comprises a semiconductor die and a bond pad formed upon the semiconductor die. The bond pad has a protrusion on a top surface of the bond pad. The package also comprises a metal contact and a bond wire coupled to the protrusion and to the metal contact.

Abstract: Embodiments disclosed herein include transistor devices and methods of forming such transistor devices. In an embodiment a transistor comprises a substrate, and a fin that extends up from the substrate. In an embodiment, the fin comprises a source region, a drain region, and a channel region between the source region and the drain region. In an embodiment, the transistor further comprises and a cavity in the fin, where the cavity is below the channel region. In an embodiment, the transistor further comprises a gate stack over the fin.

Abstract: Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.

Abstract: A method of processing a power semiconductor device includes: providing a semiconductor body with a drift region of a first conductivity type; forming a plurality of trenches extending into the semiconductor body along a vertical direction and arranged adjacent to each other along a first lateral direction; providing a mask arrangement at the semiconductor body, the mask arrangement having a lateral structure according to which some of the trenches are exposed and at least one of the trenches is covered by the mask arrangement along the first lateral direction; forming, below bottoms of the exposed trenches, a plurality of doping regions of a second conductivity type complementary to the first conductivity type; removing the mask arrangement; and extending the plurality of doping regions in parallel to the first lateral direction such that the plurality of doping regions overlap and form a barrier region of the second conductivity type adjacent to the bottoms of the exposed trenches.

Abstract: A display substrate includes: a backplane; a first electrode layer disposed on a side of the backplane; and a light-emitting layer disposed on a side of the first electrode layer away from the backplane. The light-emitting layer includes nanoparticles and a product that is obtained by an electrochemical reaction of electrochemically active groups contained in first organic ligands coordinated to the nanoparticles. The nanoparticles are cross-linked together through the product.

Abstract: A semiconductor package provided herein includes a first semiconductor die, a second semiconductor die and an insulating encapsulation. The second semiconductor die is stacked on the first semiconductor die. The insulating encapsulation laterally surrounds the first semiconductor die and the second semiconductor die in a one-piece form, and has a first sidewall and a second sidewall respectively adjacent to the first semiconductor die and the second semiconductor die. The first sidewall keeps a lateral distance from the second sidewall.

Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.

Abstract: A white light emitting material having a chemical structural formula represented by formula (I), a preparation method thereof and application thereof. The preparation method comprises subjecting tris(4-iodophenyl)amine and 4-methoxyphenylacetylene or tris(4-iodophenyl)amine and methyl 4-ethynylbenzoate to a coupling reaction under protection of a protective gas and catalysis of a Pd/Cu mixed catalyst, to obtain the white light emitting material. A novel temperature-sensitive light emitting material is synthesized through a one-step method. The material is applied to the field of diode luminescence based on the temperature-sensitive characteristic. White light luminescence can be finally realized only by reasonably controlling the temperature and duration time during heating a substrate. Compared with the existing art, the method greatly saves raw material costs and manufacturing process costs, and provides a novel idea and strategy for use of a white organic light emitting diode.