Patents Examined by Binh Tat
  • Patent number: 9270104
    Abstract: The power supply control device of the present invention includes: a set of power reception conductors; a set of power supply conductors; a set of intermediate conductors electrically connected to the set of power reception conductors, respectively; a set of relays configured to make and break electrical connections between the set of intermediate conductors and the set of power supply conductors, respectively; a zero-phase current transformer positioned to allow the set of intermediate conductors to pass through an inside of the zero-phase current transformer; a control circuit for controlling the set of relays responding to a detection result of the zero-phase current transformer; and a body block including a first block and a second block fixed to the first block. The set of power reception conductors and the set of power supply conductors are fixed to the first block. The set of intermediate conductors is fixed to the second block.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: February 23, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Noboru Inagaki, Shinichi Nakamura, Takao Akioka
  • Patent number: 9268899
    Abstract: Improved PMOS and NMOS transistor designs for sensing circuitry use in advanced nanometer flash memory devices are disclosed.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 23, 2016
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Hung Quoc Nguyen, Anh Ly, Thuan Vu
  • Patent number: 9263968
    Abstract: A bidirectional inverter-charger includes a first stage receiving or delivering energy from a line or to a load. The first stage including at least one inductor coupled with a split phase bridge. A link storage is connected between rails of a first bus and between the first stage and a second stage. The second stage includes a DC-to-DC converter connectable to a battery. The DC-to-DC converter includes a transformer providing galvanic isolation between a second bridge, connected between the rails of the first bus, and a third bridge connected between the rails of a second bus. In operation, the first stage provides power factor correction and a voltage boost while charging the battery and inverting when providing power to the line or the load. The second stage provides a controllable charge current to the battery and a voltage boost of a voltage of the battery to the link storage.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: February 16, 2016
    Assignee: EETREX, INC.
    Inventors: Dennis L. Potts, Brian Houghton
  • Patent number: 9262573
    Abstract: An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and route boundary to prevent a mismatch between a layout versus schematic (LVS) netlist and a post-simulation netlist.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Nan Yang, Chou-Kun Lin, Jerry Chang-Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang
  • Patent number: 9262557
    Abstract: The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicates that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: February 16, 2016
    Assignee: Mentor Graphics Corporation
    Inventors: Jeremy Rutledge Levitt, Christophe Gauthron, Chian-Min Richard Ho, Ping Fai Yeung, Kalyana C. Mulam, Ramesh Sathianathan
  • Patent number: 9257867
    Abstract: An externally chargeable vehicle which is charged with electric power from an external power supply includes an HV-ECU for controlling a power storage device during any of operation of the vehicle and external charging, and a PLG-ECU for controlling a charging device during external charging. With such a configuration, running and charging can be controlled while a function of the HV-ECU for controlling operation of the vehicle and a function of the PLG-ECU for external charging is prevented from becoming redundant.
    Type: Grant
    Filed: January 18, 2010
    Date of Patent: February 9, 2016
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Tomokazu Masuda, Takahiro Ito
  • Patent number: 9246350
    Abstract: A mobile terminal and a method for wirelessly charging the mobile terminal are provided. The method includes searching for a wirelessly rechargeable mobile terminal; receiving, upon finding a wirelessly rechargeable mobile terminal, power state information from the found rechargeable mobile terminal; setting the mobile terminal as one of a power supplying terminal and a power receiving terminal based on the received power state information; and performing a power charging operation with the found rechargeable mobile terminals according to the setting.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: January 26, 2016
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Hee-Won Jung, Joon-Ho Park, Eun-Tae Won, Jun-Ho Koh
  • Patent number: 9244123
    Abstract: A synchronous circuit comprises a functional circuitry and one or more validation circuits for validating synchronization of the functional circuitry. The functional and the validation circuits are clocked by a clock source. Each validation circuit comprises a clock distribution network, a test signal generator, a capture cell, a test signal path from the test signal generator to the capture cell, and a verification unit. The clock distribution network applies a launch clock signal at the test signal generator and a capture clock signal at the capture cell. The test signal generator produces a bi-level test signal. The test signal path transmits the test signal to the capture cell, which generates a proof sequence by sampling the test signal. The verification unit determines whether the proof sequence is identical to the test sequence. A method of designing a synchronous circuit and method of validating a synchronous circuit are also described.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: January 26, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Thomas Koch, Ilhan Hatirnaz, Michael Rohleder
  • Patent number: 9245074
    Abstract: A method and system to obtain a physical design of an integrated circuit from a logical design are described. The method includes performing a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget. The method also includes computing power assertions, performing a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, comparing the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, and reducing a weighting of the power assertions relative to the timing constraints based on the degradation. The executing the performing the re-synthesis, the comparing, and the reducing are done iteratively until the degradation is below a threshold value.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: January 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Pinaki Chakrabarti, Kaustav Guha, Ricardo H. Nigaglioni, Sourav Saha
  • Patent number: 9244128
    Abstract: A deep-discharge protection method for protecting a battery of a parking motor vehicle is shown. In this case, a state of charge of the battery is regularly monitored by a battery control unit and is transmitted to an evaluation unit. When a predefined state of charge of the battery is reached, a message is transmitted from a communication unit to a stored address by mobile radio and/or information acquired using a sensor system is used by the evaluation unit to determine whether a situation of the motor vehicle is suitable for autonomous recharging of the battery.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: January 26, 2016
    Assignee: Robert Bosch GmbH
    Inventor: Karsten Haug
  • Patent number: 9223368
    Abstract: The disclosure relates to a countermeasure method in an electronic microcircuit, comprising successive process phases executed by a circuit of the microcircuit, and adjusting a power supply voltage between power supply and ground terminals of the circuit, as a function of a random value generated for the process phase, at each process phase executed by the circuit.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: December 29, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Mathieu Lisart, Fabrice Marinet
  • Patent number: 9216654
    Abstract: An electric vehicle charging apparatus is disclosed. The electric vehicle charging apparatus has a housing having a front cavity, rear cavity, and a separating wall having a common electrical passage, wherein the rear cavity is formed by sidewalls with one sidewall having a slot formed therein. A power cord passes through the common electrical passage in the separating wall, and the power cord is configurable to provide a number of electrical connection options, such as an “outside cord option” and a “rear mount option.” Methods of configuring the electric vehicle charging apparatus are provided, as are other aspects.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: December 22, 2015
    Assignee: Siemens Industry, Inc.
    Inventor: Timothy Biedrzycki
  • Patent number: 9218447
    Abstract: Crosstalk effects can be taken into account in automatic test pattern generation (ATPG) by providing crosstalk fault models, determining paths and/or nodes to be sensitized to activate each crosstalk fault, and optimizing to enable as many crosstalk faults as possible with a given pattern, subject to constraints. Constraints can include threshold numbers of endpoints/observation points and/or attempts to sensitize. Intermediate nodes in a crosstalk fault model path to an observation point can also be determined and/or sensitized.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: December 22, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kanad Basu, Raghu Gaurav GopalaKrishnaSetty, Hari Krishnan Rajeev
  • Patent number: 9211800
    Abstract: A battery system includes a first battery and a second battery connected in parallel and performing charge and discharge. A first relay is switched between an ON state in which the charge and discharge of the first battery are allowed and an OFF state in which the charge and discharge of the first battery are prohibited. A second relay is switched between an ON state in which the charge and discharge of the second battery are allowed and an OFF state in which the charge and discharge of the second battery are prohibited. A controller controls the ON state and the OFF state of each of the first relay and the second relay. The controller also changes the order in which the first relay and the second relay are switched to the ON state, in performing the charge and discharge of the first battery and the second battery.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: December 15, 2015
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yuji Nishi, Shunsuke Fujii
  • Patent number: 9213800
    Abstract: The optical proximity correction verification method includes loading a layout data to be verified to a processor, loading a reference layout data to the processor. The processor performs a first stage Boolean operation on the layout data to be verified to generate first verified data. The processor performs a layout versus layout verification on the first verified data to generate second verified data by using the reference layout data. If the layout versus layout verification is successfully performed, the processor performs a second stage Boolean operation on the second verified data to generate third verified data. By using the reference layout data, the processor performs a Boolean check on the third verified data to generate fourth verified data.
    Type: Grant
    Filed: August 31, 2014
    Date of Patent: December 15, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Chih Chang, Kuo-Hsun Huang, Chao-Yao Chiang
  • Patent number: 9209633
    Abstract: A charging apparatus is provided with a connector, a pair of power lines, a charger, a holding part and a controller. The connector has a pair of connection terminals electrically connectable to an object to be charged. The power lines electrically connected to the connection terminals. The charger is connected to the power lines for charging the object to be charged. The holding part holds the connector. The controller is programmed to determine the conduction state on the power lines and the connection terminals. The holding part has a conduction part for bringing about conduction through the connection terminals.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: December 8, 2015
    Assignee: Nissan Motor Co., Ltd.
    Inventor: Masahiro Bandai
  • Patent number: 9208281
    Abstract: Methods and systems for optimizing and/or designing integrated circuits. One exemplary method includes determining fanout of a driving component in a representation of an integrated circuit (IC) being designed, determining for the driving component, the loads in the representation of the IC driven by the driving component, and determining use of existing wiring resources used to connect the loads to the driving component. The method further includes optimizing, based on the use of existing wiring resources, the fanout of the driving component, and the loads being driven by the driving component, a design of the IC.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: December 8, 2015
    Assignee: Synopsys, Inc.
    Inventors: Jovanka Ciric Vujkovic, Kenneth S. McElvain
  • Patent number: 9202006
    Abstract: The present disclosure relates to a computer-implemented method for visualization in an electronic design. The method may include providing an electronic design and receiving a selection of at least one pin associated with the electronic design at a first graphical user interface. The method may further include generating a stub for each of the selected pins at the first graphical user interface. The method may also include providing a second graphical user interface configured to allow for the assignment of a signal name to each stub. The method may include extending the stub for each of the selected pins to reach a target destination associated with the electronic design. The method may also include displaying the signal name for each stub on at least one of the first graphical user interface and the second graphical user interface.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: December 1, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Utpal Bhattacharya, Vikas Kohli
  • Patent number: 9203261
    Abstract: An excavator includes an electric load, an electrical energy storage unit including an electrical energy storage part (19) that supplies electric power to the electric load, and a control unit (30) that controls an amount of charge to the electrical energy storage part (19) so that a charge rate of the electrical energy storage part (19) is between a system control upper limit value and a system control lower limit value. The control unit (30) controls the amount of charge to the electrical energy storage part (19) based on a changing trend of a detection value of the charge rate.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: December 1, 2015
    Assignee: SUMITOMO HEAVY INDUSTRIES, LTD.
    Inventor: Yuta Sugiyama
  • Patent number: 9202004
    Abstract: The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include providing an electronic design including, at least in part, one or more hardware description languages and one or more software programming languages. Embodiment may also include calculating, using one or more processors, configuration information without analyzing the electronic design, wherein the configuration information includes one or more memory elements configured to control a mode of operation of the electronic design. Embodiments may further include storing a seed for each configuration, wherein each seed may be configured to cause a constraint solver to set a defined set of values for one or more random variables in a class associated with the seed.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: December 1, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Daniel A. Cohen, John LeRoy Pierce, Nir Weiss