Abstract: A rechargeable battery module including a plurality of battery cells connected in series, a charging transistor, a balancing circuit and a control chip. The charging transistor is operative to convey a charging current to charge the battery cells. Based on voltage levels of the battery cells, the control chip disables the charging transistor and controls the balancing circuit to perform a first stage battery balance process. After finishing the first stage battery balance process, the control chip enables the charging transistor to charge the battery cells again. After being switched to a constant voltage charging mode, the control chip controls the balancing circuit based on the voltage levels of the battery cells to perform a second stage battery balance process.

Abstract: This disclosure relates generally to field-programmable gate arrays (FPGAs). Some implementations relate to methods and systems for partitioning FPGA circuit designs to facilitate certification. In one aspect, a method includes generating a hardware description language (HDL) implementation of a circuit design. The method additionally includes partitioning the design into a first portion and a second portion. In some implementations, the second portion corresponds to a safety-critical portion of the design while the first portion corresponds to a non-safety-critical portion. The method additionally includes generating first configuration settings for the first portion and generating second configuration settings for the second portion. The method additionally includes verifying, or providing to a third-party certification body for verification, the first configuration settings for the first portion and the second configuration settings for the second portion.

Abstract: A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.

Abstract: Disclosed are methods, systems, and articles of manufactures for implementing a physical design with force directed placement or floorplanning and layout decomposition by identifying multiple nodes and then iteratively generating multiple cells by using the multiple nodes in a decomposition process and applying force model(s) to iteratively morph the cells until convergence criteria are satisfied to generate a layout or floorplan of an electronic design without requiring complete conductivity for the electronic design. The initially identified custom conductivity information is maintained throughout this iterative process.

Abstract: A method for modeling metal routing includes extracting physical parameters of a metal interconnect for a circuit design, determining a resistance value from a database of metal interconnects with the extracted physical parameters, the resistance value being at a maximum frequency of a frequency range to be simulated, modeling the interconnect with a symmetric lumped transmission line model, and defining a resistance value of the lumped transmission line model to be about 1.05-1.3 times the resistance value taken from the database.

Abstract: A method and system for generating and matching complex series and/or parallel combinations of nominally identical initial elements to achieve an arbitrary compound value is disclosed. A recursive algorithm successively adds one or more similar nominal two-terminal elements to generate a series and/or parallel compound combination of nominal elements, the compound combination having a desired impedance. The compound value, and thus the ratio between two compound values, can be determined to almost any desired degree of accuracy, with potential errors greatly reduced from those typical in the construction of individual elements of different values. Since the initial elements are nominally identical, the compound value, and the ratio between values, depends primarily upon the connections of the initial elements, rather than their geometry, and thus remain virtually constant regardless of variations in the manufacturing process.

Abstract: A method and NoC design tool is disclosed that automatically maps the paths listed in a timing report and the unit size in an area report to the topology of a NoC and displays the paths and unit sizes in a GUI. The tool can also automatically add pipeline stages, separated by the maximum delay allowed in the timing budget, in order to achieve timing closure in an automated way.

Abstract: An dual function distance metric for pattern matching based hotspot clustering is described. The dual function distance metric can handle patterns containing multiple polygons, is easy to compute, and is tolerant of small variations or shifts of the shapes. Compared with an XOR distance metric pattern clustering, the dual function distance metric can achieve up to 37.5% accuracy improvement with 2×-4× computational cost in the context of cluster analysis. The dual function distance metric is reliable and accurate for characterizing clips (e.g. hotspots), thereby making it desirable for industry applications.

Abstract: A Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to the Test Wrappers via an interconnect fabric. The Test Wrappers employ one or more test ports to provide test data, control, and/or stimulus signals to the IP block to facilitate circuit-level testing of the IP block. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric.

Abstract: A method of determining stitching errors in multiple lithographically exposed fields on a semiconductor layer during a semiconductor manufacturing process is provided. The method may include receiving a predetermined design distance corresponding to a plurality of petals associated with the multiple lithographically exposed fields and identifying a blossom within a single field-of-view (FOV) of a metrology tool, where the blossom is formed by a non-overlapping abutment of corners corresponding to the multiple lithographically exposed fields. The blossom may include the plurality of petals associated with the multiple lithographically exposed fields. Petal position errors may then be calculated based on both a coordinate position for each of the plurality of petals within the blossom and the predetermined design distance, whereby the calculated petal position errors are indicative of stitching errors for the multiple lithographically exposed fields.

Abstract: A hierarchical battery-management system mainly comprises a monitoring and equalizing module, an intermediary module, and a decision and communication module. The monitoring and equalizing module electrically couples with the battery cells, the intermediary modules electrically couple with the monitoring and equalizing module and the decision and communication module. The decision and communication module electrically couples with a power system or an electronic/electrical apparatus, and a hierarchical management structure constructed by the intermediary module to screen data and to transmit meaningful cell data to meet real time managing requirements of the large battery set.

Abstract: Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed patterns of crossing elongate features with pillars at the intersections. Spacers are simultaneously applied to sidewalls of both sets of crossing lines to produce a pitch-doubled grid pattern. The pillars facilitate rows of spacers bridging columns of spacers.

Abstract: A manufacturing method of microstructure comprises steps of: a motion determination step which determines the motion of a substrate relative to at least a photomask; a microlens determination step which determines the profile of a microlens unit on the substrate; an analysis step which calculates the feature of the photomask according to the motion of the substrate and the profile of the microlens unit by using a numerical analysis method; a production step which produces the photomask according to the feature of the photomask; driving the substrate to do the motion determined in the motion determination step, and meanwhile making a laser light illuminate the substrate through the photomask to manufacture the microlens unit on the substrate by the superposition effect of the laser light; and performing a photolithography process by using the microlens unit to produce a microstructure on a photoresist substrate.

Abstract: An electronic device is provided. When the electronic device is at a power exhaustion state and a first external device with a charging function is coupled to a connection interface to provide a first supply voltage to a power pin of the connection interface, a voltage regulation unit transforms the first supply voltage to a first operation voltage, and a storage unit powered by the first operation voltage outputs device information of the electronic device to the first external device through a signal transmitting/receiving pin set of the connection interface. When the first external device provides a second supply voltage to the power pin in response to the device information, the electronic device enters a charging mode. In the charging mode, the charging unit provides a charging voltage according to the second supply voltage to charge the battery unit and provides a second operation voltage to a processing unit.

Abstract: Some embodiments relate to a method for pre-coloring data within an integrated chip layout to avoid overlay errors that result from mask misalignment during multiple patterning lithography. The method may be performed by generating a graphical IC layout file containing an integrated chip layout having a plurality of IC shapes. The IC shapes within the graphical IC layout file are assigned a color during decomposition. The IC shapes are further pre-colored in a manner that deliberately assigns the pre-colored data to a same mask. During mask building data associated with IC shapes that have been pre-colored is automatically sent to a same mask, regardless of the colors that are assigned to the shapes. Therefore, the pre-colored shapes are not assigned to a masked based upon a decomposition, but rather based upon the pre-coloring. By assigning IC shapes to a same mask through pre-coloring, overlay errors can be reduced.

Abstract: A power supply device includes a plurality of power supply units connected in parallel, and includes a positive electrode-side junction formed by the joining of positive electrode-side terminals of the plurality of power supply units and a negative electrode-side junction formed by the joining of negative electrode-side terminals of the plurality of power supply units. Each of the plurality of power supply units includes a battery unit, and a first relay that is provided between one of the positive and negative electrode-side junctions and the battery unit and is electrically disconnectably connected in series to the battery unit. Each of the plurality of power supply units includes a resistive element of which one end is connected between the first relay, which is connected to one of a positive electrode terminal and a negative electrode terminal of the battery unit, and the battery unit.

Abstract: An approach is provided in which an equivalence class generator selects a configurable module that includes control points and configuration parameters. The configuration parameters define a parameter state space of the configurable module. The equivalence class generator utilizes the control points to generate equivalence classes, which include class representatives that indicate values for the configuration parameters. Next, one of the class representatives are selected and verified from each of the equivalence classes. In turn, the verification of the class representatives verifies the parameter state space of the configurable module.

Abstract: Techniques for using subcell libraries allow efficient handling of a large number of cells. To improve design accuracy using cell libraries, very large cell libraries are needed. However, optimization tools are not able to use very large cell libraries directly, since their results suffer. Very large cell libraries are organized into sublibraries that are adapted to be processed by optimization tools. This allows improvement in the design quality of integrated circuits, while allowing the designs to be processed by optimization tools.

Abstract: Disclosed is a method and system for clock tree construction across clock domains, an integrated circuit and fabrication method thereof. A method for clock tree construction includes acquiring a netlist describing an integrated circuit (IC), comprising data for describing physical locations and logic connections of clock sinks belonging to multiple clock domains on the pattern of the IC, and constructing the clock tree across clock domains based on the netlist, such that clock cells belonging to different clock domains can share more physical locations. Accordingly, clock trees can be constructed across clock domains to improve IC performance.

Abstract: A storage battery has at least battery banks, switching units, a charging terminal, a discharging terminal and a battery management unit. The battery banks form a bank structure. Each switching unit electrically connects a group of the battery banks with either the charging terminal or the discharging terminal, and disconnects the group of the battery banks from the charging terminal or the discharging terminal. The battery management unit instructs the switching units to electrically and simultaneously connect one or more battery banks to the charging terminal during charging, and to electrically and simultaneously connect one or more battery banks to the discharging terminal during discharging.