Abstract: A design verification workstation contains both debug and constraint solver capabilities during simulation of a design under test. The design verification workstation is configured to allow the user to debug constraints, stop the constraint solver, navigate problems and variables, and make modifications on-the fly during the simulation to constraint information. Additionally, in some embodiments, the design verification workstation may allow a user to use a constraint solver to experiment if the modifications will lead to desired test stimulus. Since this debug process happens during simulation, users do not need to recompile the test case. Additionally, once a user is satisfied with the modifications made to the simulation, the modification could be saved for future usage.

Abstract: An aspect provides a method, including: normally discharging one or more battery cells housed in a flexible exterior material; determining one or more of the one or more battery cells has less than a predetermined voltage level; and actively discharging the one or more battery cells determined to have less than the predetermined voltage. Other aspects are described and claimed.

Abstract: Systems and techniques for computing a timing effort metric are described. According to one definition, the computed timing effort metric indicates a level of difficulty of fixing a timing violation associated with a timing path between two circuit objects in a circuit design layout.

Abstract: A system and method for an automated way of running spice on a small portion of a design is presented. The system includes a sub-circuit netlist generation processor and an analog simulation processor. The sub-circuit netlist generation processor generates a sub-circuit netlist based, at least in part, on a HDL netlist, a parasitic capacitance database and trace rules. The sub-circuit netlist contains significantly fewer paths than the HDL netlist of an entire design so that its simulation time is much quicker. The analog simulation processor generates analog simulation results of the sub-circuit netlist based, at least in part, on dynamic inputs.

Abstract: A reversible buck or boost converter is operable in a buck mode and in a boost mode. In the buck mode, the converter receives a supply voltage via an input terminal and generates a charging current that is supplied to a battery, thereby charging the battery. The supply voltage is also supplied through the converter to an output terminal. In a boost mode, the converter receives power from the battery and generates a supply current and voltage that is output onto the output terminal. The same single current sense resistor is used both to control the charging current in the buck mode and to control a constant current supplied to the output terminal in the boost mode. The output current is controlled to be constant, regardless of changes in the in the battery voltage and changes in the output voltage.

Abstract: Provided is a vehicle charging device (170) that uses a power source (101) outside of a vehicle (160) to charge a battery (115) installed in the vehicle (160). A charger (114) charges the battery (115). A voltage measurement unit (111) measures the input voltage corresponding to the input current in the charger (114). A current measurement unit (112) measures the input current (Ic) in the charger (114). A control unit (113) changes the input currents (Ic) of the charger (114) into a plurality of values, and controls the input current (Ic) when the input voltage (Vc) has changed, according to the corresponding relationship between the input currents (Ic), when each has been changed, and the measured input voltages (Vc).

Abstract: A battery management circuit for managing a battery apparatus is provided. The battery apparatus includes at least a first battery unit and a second battery unit connected in parallel. The battery management circuit includes a detection circuit and an adjustment circuit. The detection circuit is arranged to detect a voltage relationship between the first and second battery units to generate a first detection result. The adjustment circuit is coupled to the detection circuit. When the voltage relationship does not meet a predetermined voltage condition, the adjustment circuit is arranged to adjust a voltage of at least one of the first and second battery units in order to make the voltage relationship meet the predetermined voltage condition.

Abstract: A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape.

Abstract: Pattern matching technology is used to find locations in mask data that are available for later processes, such as marking. These locations are found using pattern definitions. A match algorithm outputs locations that match the pattern definitions. Each pattern definition may include multiple marks. The patterns can be symmetrical or asymmetrical and the marks can be correctly placed during a marking step by using orientation information determined during the pattern matching process. Large area geometries may be located by a two-step process that generates a pattern definition by defining smaller patterns therein and by defining the spatial relationships of the smaller patterns. An additional correlation step results in high accuracy while minimizing computing resources.

Abstract: A method for performing battery balancing control with aid of pluggable mechanism is provided. The method is applied to a power supply device. The method includes the steps of: providing a pluggable external module, wherein the pluggable external module includes a first connection port, and further includes a set of external balancing circuits corresponding to a set of battery cells of a specific battery module within the power supply device, respectively; and on a case of the specific battery module, providing a second connection port corresponding to the first connection port, allowing the pluggable external module to be coupled to the specific battery module with aid of the pluggable mechanism formed with the first connection port and the second connection port, in order to utilize the set of external balancing circuits to perform balancing operations on the set of battery cells. Associated apparatuses are further provided.

Abstract: This disclosure relates to a method of making a semiconductor device. The method includes comparing a schematic design of the semiconductor device to a layout design of the semiconductor device. The method further includes generating layout style information based on the layout design and generating array edge information based on the layout design and the schematic design. The method further includes selectively revising the layout design using smart dummy insertion using the layout style information and the array edge information. The method further includes performing a design rule check on the revised layout design using the layout style information and the array edge information. This disclosure also relates to a system for making a semiconductor device and a semiconductor device.

Abstract: A battery pack and a method for controlling charge-and-discharge of the battery pack by its thermoelectric property are provided, in which the battery pack has a plurality of thermal regions divided by different ranges of temperature. The battery pack includes a plurality of parallel-connected battery groups and a plurality of variable resistances. The parallel-connected battery groups are located in the thermal regions respectively, and each of the parallel-connected battery groups includes batteries connected in parallel. The variable resistances are disposed between two parallel-connected battery groups.

Abstract: A balancing circuit for balancing battery units includes a control unit, an inductor unit and an energy transfer unit. The control unit is coupled to at least one battery unit of the battery units. The control unit includes at least one switch device. The inductor unit is coupled between the switch device and the battery unit, and is arranged for taking away an excess energy of the battery unit according to a switch state of the switch device, and accordingly generating an inductive energy corresponding to the excess energy. The energy transfer unit is coupled to the inductor unit, and is arranged for providing the inductive energy to the battery units and storing the inductive energy.

Abstract: A balancing circuit for balancing battery units includes balancing modules. Each of the balancing modules includes a first and a second switch unit, and a first and a second inductive device, wherein the first inductive device is coupled to the second inductive device. The balancing modules include a first and a second balancing module, respectively coupled to a first and a second battery unit of the battery units. The first inductive device of the first balancing module takes away an excess energy of the first battery unit according to a switch state of the first switch unit of the first balancing module, and stores an inductive energy corresponding to the excess energy in the second balancing module. The second inductive device of the second balancing module provides the inductive energy for the second battery unit according to a switch state of the second switch unit of the second balancing module.

Abstract: Systems and methods for functionally verifying the performance of a system on a chip (SOC) are provided herein. According to some embodiments, the methods may include at least the steps of analyzing a verification log, via a functional verification system, to determine signatures by correlating a pattern of at least one of triggered and untriggered assertions in one or more blocks of a plurality of blocks to behaviors of at least one of the SOC and the one or more blocks of the plurality of blocks. Exemplary methods also include categorizing signatures according to the behaviors, and storing similar signatures based upon the categorization in a database.

Abstract: Disclosed are improved methods, systems, and computer program products for implementing an interface for visualizing, generating, and optimizing an I/O ring arrangement for an electronic design. A ribbon-based interface may be employed to visually see and control the design of the I/O ring.

Abstract: A collection, charging and distribution machine collects, charges and distributes portable electrical energy storage devices (e.g., batteries, super- or ultracapacitors). To charge, the machine employs electrical current from an external source, such as the electrical grid or an electrical service of an installation location. The machine determines a first number of devices to be rapidly charged, employing charge from a second number of devices identified to sacrifice charge. Thus, some devices may be concurrently charged via current from the electrical service and current from other devices, to achieve rapid charging of some subset of devices. The devices that sacrifice charge may later be charged. Such may ensure availability of devices for end users.

Abstract: A method of designing a fin field effect transistor (FinFET)-based circuit includes designing, using a processor, a first circuit schematic design based on a performance specification, the first circuit schematic design is free of artificial elements, wherein the artificial elements are used to simulate electrical performance of the FinFET-based circuit. The method further includes modifying, using the processor, at least one device within the first circuit schematic design to form a second circuit schematic design taking the artificial elements into consideration. The method further includes performing a pre-layout simulation using the second circuit schematic and taking the artificial elements into consideration. The method further includes generating a layout, wherein the layout does not take the artificial elements into consideration, and performing a post-layout simulation, wherein the post-layout simulation does not take the artificial elements into consideration.

Abstract: Method of configuring a rotating electric machine (1) stator (2), comprising the following steps: employing a stator (2) having a carcass (5) on which electrical conductors are coiled so as to form N coils (6j), N being greater than or equal to four and, electrically connecting the coils (6j) to an electrical power supply device (7) in such a way that each coil (6j) is traversed by a specific electric current (ij) delivered by the electrical power supply device (7), the connection of the stator (2) to the electrical power supply device (7) being performed in such a way that as one progresses around the axis (X) of the stator away from a reference coil (61), the phase shift between the current (i1) traversing the said reference coil and the current (ij) traversing each of the other coils (6j) and specific to the latter varies in a strictly monotonic manner as one progresses.

Abstract: A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.