Abstract: A memory cell comprises a first feature and a second feature. The second feature comprises a dielectric material and defines an opening at least partially overlying the first feature. A third feature is formed on the first feature and partially fills the opening in the second feature. What is more, a phase change material at least fills a volume between the second feature and the third feature. At least a portion of the phase change material is operative to switch between lower and higher electrical resistance states in response to an application of a switching signal to the memory cell.

Abstract: A semiconductor device including a multilevel wiring with a small interwiring capacitance is provided by comprising a wiring, a conductive film formed on an upper surface of the wiring to prevent diffusion of a wiring material, and an insulating film which is constituted of low dielectric constant insulating films stacked to form at least two layers, an interface thereof being positioned in a side face of the wiring.

Abstract: Methods of fabricating a phase change memory device having a small area of contact are provided. The method includes forming a lower interlayer insulating layer on a semiconductor substrate, and forming a lower conductor pattern within the lower inter-insulating layer. A first insulating layer pattern which crosses a top surface of the lower conductor pattern is formed on the semiconductor substrate having the lower conductor pattern. A conductive spacer pattern electrically connected to the lower conductor pattern is formed on a sidewall of the first insulating layer pattern. A first interlayer insulating layer is formed on the semiconductor substrate having the conductive spacer pattern. The first interlayer insulating layer and the conductive spacer pattern are planarized to form a bottom electrode. A second insulating layer pattern which crosses a top surface of the bottom electrode and exposes a portion of the bottom electrode is formed on the semiconductor substrate having the bottom electrode.

Abstract: A nitride semiconductor laser device has a nitride semiconductor substrate that includes a dislocation-concentrated region 102 and a wide low-dislocation region and that has the top surface thereof slanted at an angle in the range of 0.3° to 0.7° relative to the C plane and a nitride semiconductor layer laid on top thereof. The nitride semiconductor layer has a depression immediately above the dislocation-concentrated region, and has, in a region thereof other than the depression, a high-quality quantum well active layer with good flatness and without cracks, a layer that, as is grown, readily exhibits p-type conductivity, and a stripe-shaped laser light waveguide region. The laser light waveguide region is formed above the low-dislocation region. This helps realize a nitride semiconductor laser device that offers a longer life.

Abstract: A ZnO asperity-covered carbon nanotube (CNT) device has been provided, along with a corresponding fabrication method. The method comprises: forming a substrate; growing CNTs from the substrate; conformally coating the CNTs with ZnO; annealing the ZnO-coated CNTs; and, forming ZnO asperities on the surface of the CNTs in response to the annealing. In one aspect, the ZnO asperities have a density in the range of about 100 to 1000 ZnO asperities per CNT. The density is dependent upon the deposited ZnO film thickness and annealing parameters. The CNTs are conformally coating with ZnO using a sputtering, chemical vapor deposition (CVD), spin-on, or atomic layer deposition (ALD). For example, an ALD process can be to deposit a layer of ZnO over the CNTs having a thickness in the range of 1.2 to 200 nanometers (nm).

Abstract: A P-N junction device and method of forming the same are disclosed. The P-N junction device may include a P-N diode, a PiN diode or a thyristor. The P-N junction device may have a monocrystalline or polycrystalline raised anode. In one embodiment, the P-N junction device results in a raised polycrystalline silicon germanium (SiGe) anode. In another embodiment, the P-N junction device includes a first terminal (anode) including a semiconductor layer positioned above an upper surface of a substrate and a remaining structure positioned in the substrate, the first terminal positioned over an opening in an isolation region; and a second terminal (cathode contact) positioned over the opening in the isolation region adjacent the first terminal. This latter embodiment reduces parasitic resistance and capacitance, and decreases the required size of a cathode implant area since the cathode contact is within the same STI opening as the anode.

Abstract: One or more LED dice are mounted on a support structure. The support structure may be a submount with the LED dice already electrically connected to leads on the submount. A mold has indentations in it corresponding to the positions of the LED dice on the support structure. The indentations are filled with a liquid optically transparent material, such as silicone, which when cured forms a lens material. The shape of the indentations will be the shape of the lens. The mold and the LED dice/support structure are brought together so that each LED die resides within the liquid silicone in an associated indentation. The mold is then heated to cure (harden) the silicone. The mold and the support structure are then separated, leaving a complete silicone lens over each LED die. This over molding process may be repeated with different molds to create concentric shells of lenses. Each concentric lens may have a different property, such as containing a phosphor.

Abstract: Bottom electrodes of memory cell capacitors are recessed to prevent electrical shorts between neighboring memory cells. A partially fabricated memory cell capacitor has a bottom electrode comprising titanium nitride (TiN) and hemispherical grained (HSG) silicon. The container housing the capacitor is filled with photoresist and then planarized. The TiN layer is then selectively recessed with a peroxide mixture and subsequently the HSG silicon layer is recessed using tetramethyl ammoniumhydroxide. Thus, the bottom electrode is recessed below the level of particles which may overlie the memory cell capacitors and cause shorts by contacting the bottom electrode.

Abstract: A semiconductor substrate has a cell region and a peripheral circuit region surrounding the cell region. In the cell region a plurality of lower electrodes are connected to a conductive region of the semiconductor substrate, and are arrayed along row and column directions. A dielectric layer is formed on the plurality of lower electrodes. An upper electrode is formed on the dielectric layer, entirely covering the cell region, and is formed extending to a portion of the peripheral circuit region that has a step coverage lower by a height of the lower electrode than the cell region. An edge of the upper electrode has square-shaped projections that are distanced from each other at a uniform interval and are repetitively arrayed. With the described structure, pattern defects can be sensed and controlled, preventing and substantially reducing process defect.

Abstract: The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and/or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordance with one embodiment of the disclosure CMOS devices on SOI regions are manufactured on semiconductors having different orientations. According to another embodiment, an SOI device is contemplated as having a plurality of semiconductor regions having at least one of a different semiconductor material, crystalline lattice constant or lattice strain. Methods and processes for fabricating the different embodiments of the invention is also disclosed.

Abstract: Transistors and manufacturing methods thereof are disclosed. An example transistor includes a semiconductor substrate divided into device isolation regions and a device active region. The example transistor includes a gate insulating film formed in the active region of the semiconductor substrate, a gate formed on the gate insulating film, a channel region formed in the semiconductor substrate and overlapping the gate, and LDD regions formed in the semiconductor substrate and at both sides of the gate, centering the gate. In addition, the example transistor includes source and drain regions formed under the LDD regions, offset regions formed in the semiconductor substrate and between the channel region and LDD regions, and gate spacers formed at both sidewalls of the gate.

Abstract: Bottom electrodes of memory cell capacitors are recessed to prevent electrical shorts between neighboring memory cells. A partially fabricated memory cell capacitor has a bottom electrode comprising titanium nitride (TiN) and hemispherical grained (HSG) silicon. The container housing the capacitor is filled with photoresist and then planarized. The TiN layer is then selectively recessed with a peroxide mixture and subsequently the HSG silicon layer is recessed using tetramethyl ammoniumhydroxide. Thus, the bottom electrode is recessed below the level of particles which may overlie the memory cell capacitors and cause shorts by contacting the bottom electrode.

Abstract: A method for etching a dielectric layer over a substrate is provided. A photoresist mask is formed over the dielectric layer. The substrate is placed in a plasma processing chamber. An etchant gas comprising NF3 is provided into the plasma chamber. A plasma is formed from the NF3 gas. The dielectric layer is etched through the photoresist mask with the plasma from the NF3 gas.

Abstract: A multiple layer tunnel insulator is fabricated between a substrate and a discrete trap layer. The properties of the multiple layers determines the volatility of the memory device. The composition of each layer and/or the quantity of layers is adjusted to fabricate either a DRAM device, a non-volatile memory device, or both simultaneously.

Abstract: A method for manufacturing a bottom substrate of a liquid crystal display device by using only three masks is disclosed. The method includes the following steps. First, a patterned first metal layer, an insulating layer, a semiconductor layer and a second metal layer are formed subsequently on a substrate. Afterwards, the second metal layer is manufactured to have two different thicknesses by using a photolithographic process. After that, a planar layer is formed on the second metal layer and then the planar layer is etched until part of the second metal layer is exposed. Finally, a patterned transparent electrode layer is formed on the second metal layer.

Abstract: A method of fabricating wafer level package is provided. First, a wafer having a front and a rear surfaces is provided. Several fosses are then formed on the front surface of the wafer. Next, an insulative layer is formed on a surface of each fosse; a conductive layer is then formed on part of the front surface of the wafer and the insulative layer of each fosse. A solder layer is formed on the conductive layer above each fosse. Afterward, a first substrate is attached to the front surface. Several holes are formed on the rear surface, and the holes baring the solder layer are positioned corresponding to the fosses. Then, a second substrate is attached to the rear surface of the wafer. The second substrate has several conductive pillars correspondingly inserted into the holes for connecting the solder layers. Next, the conductive structures are formed on the second substrate.

Abstract: Flash memory and methods of fabricating flash memory are disclosed. A disclosed method comprises: forming a first floating gate; and extending the first floating gate by forming a second floating gate adjacent a first sidewall of the floating gate. The second floating gate extends upward above the first floating gate. The method also includes depositing a dielectric layer on the first floating gate and the second floating gate; and forming a control gate on the dielectric layer.

Abstract: Nano-engineered structures are disclosed, incorporating nanowhiskers of high mobility conductivity and incorporating pn junctions. In one embodiment, a nanowhisker of a first semiconducting material has a first band gap, and an enclosure comprising at least one second material with a second band gap encloses said nanoelement along at least part of its length, the second material being doped to provide opposite conductivity type charge carriers in respective first and second regions along the length of the of the nanowhisker, whereby to create in the nanowhisker by transfer of charge carriers into the nanowhisker, corresponding first and second regions of opposite conductivity type charge carriers with a region depleted of free carriers therebetween. The doping of the enclosure material may be degenerate so as to create within the nanowhisker adjacent segments having very heavy modulation doping of opposite conductivity type analogous to the heavily doped regions of an Esaki diode.

Abstract: A surface-spintronic device operating on a novel principles of operations may be implemented as a spin conducting, a spin switching or a spin memory device. It includes a magnetic atom thin film (13) layered on a surface of a solid crystal (12) and a drain and a source electrodes (14)and (15) disposed at two locations on the magnetic atom thin film, respectively, whereby a spin splitting surface electronic state band formed in a system comprising said solid crystal(12) surface and said magnetic atom thin film (13) is utilized to obtain a spin polarized current flow. With electrons spin-polarized in a particular direction injected from the source electrode (15), controlling the direction of magnetization of the magnetic atom thin film (13) allows switching on and off the conduction of such injected electrons therethrough.

Abstract: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.