Patents Examined by Bradley W. Baumeister
  • Patent number: 6617606
    Abstract: A light-emitting diode having an excellent high-speed response characteristic and capable of giving a large light output with a small variation of the light output during the operation is provided. In the light-emitting diode, an active layer comprising a single quantum well layer of p-type Ga0.51In0.49P, a lower barrier layer of p-type (Al0.5Ga0.5)0.51In0.49P and an upper barrier layer of p-type (Al0.5Ga0.5)0.51In0.49P is highly doped with p-type dopant (Zn, Mg, Be, C) or n-type dopant (Si, Se, Te) to produce non-radiative recombination level in the upper and lower barrier layers. Carriers injected into the quantum well layer not only recombine radiatively therein and also recombine nonradiatively at boundaries of the upper barrier layer and the lower barrier layer, remarkably increasing recombination velocity of carriers and dramatically improving the response characteristic.
    Type: Grant
    Filed: September 10, 2001
    Date of Patent: September 9, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Nakatsu, Takahisa Kurahashi, Tetsurou Murakami, Shouichi Ohyama
  • Patent number: 6617618
    Abstract: A light emitting semiconductor device, comprising: a lower cladding layer of AlzGa1-zAs (0<z≦1) alloy semiconductor layers, having a first conductivity type; a lower light guide layer of AlzGa1-zAs (0<z≦1) alloy semiconductor layers, having a band gap narrower than that of the lower cladding layer; a lower spacing layer, comprising at least one molecular layer of GaAs; a GaxIn1-xNyAs1-y (0≦x≦1 and 0<y<1) active layer, having a thickness less than the critical thickness so as not to give rise to misfit dislocations and having a band gap narrower than that of the lower light guide layer; an upper spacing layer, comprising at least one molecular layer of GaAs; an upper light guide layer of AlzGa1-zAs (0<z≦1) alloy semiconductor layers, having a band gap narrower than that of the active layer and narrower than that of the lower cladding layer; and an upper cladding layer of AlzGa1-zAs (0<z≦1) alloy semiconductor layers, having a second conductivity type, each grown on a
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: September 9, 2003
    Assignee: Ricoh Company Ltd.
    Inventor: Shunichi Sato
  • Patent number: 6614046
    Abstract: A nuclear spin control device comprises a first semiconducting layer with spin-up carriers, a second semiconducting layer with spin-down carriers; and a third semiconducting layer arranged between the first and the second semiconducting layers. The third semiconducting layer can be tunnelled selectively by the spin-up carriers and the spin-down carriers such that nuclear spin in the third semiconducting layer selectively interacts with the carriers so as to be oriented into a desired direction. The device may be adapted to control the shape of a wave function so as to cover nuclear spins in the third semiconducting layer and propagate information of one nuclear spin to another nuclear spin.
    Type: Grant
    Filed: February 12, 2001
    Date of Patent: September 2, 2003
    Assignee: Tohoku University
    Inventors: Hideo Ohno, Yuzo Ohno, Shuya Kishimoto
  • Patent number: 6608330
    Abstract: First and second well layers of a light emitting device emit light of different peak wavelengths so as to produce a mixed light, such as white light having high luminous intensity and high luminous efficiency. A color rendering property of the device can be controlled by adjusting the ratio of the growth numbers of the first and second well layers, and/or the thickness of the barrier layers sandwiching the well layers. The color rendering property can also be controlled by forming the second well layer so as to have a degree of asperity greater than that of the first well layer, or so that a degree of area occupied by dished portions having a thickness which is less than half of an average thickness over a total surface is not less than 10%.
    Type: Grant
    Filed: September 21, 1999
    Date of Patent: August 19, 2003
    Assignee: Nichia Corporation
    Inventor: Motokazu Yamada
  • Patent number: 6552412
    Abstract: A semiconductor device of a pin junction structure, constituted by a quantum-wave interference layers Q1 to Q4 with plural periods of a pair of a first layer W and a second layer B and middle layers (carrier accumulation layers) C1 to C3. The second layer B has wider band gap than the first layer W. Each thicknesses of the first layer W and the second layer B is determined by multiplying by an odd number one fourth of wavelength of quantum-wave of carriers conducted in the i-layer in each of the first layer W and the second layer B existing at the level near the lowest energy level of the second layer B. A &dgr; layer, for sharply varying energy band, is formed at an every interface between the first layer W and the second layer B and has a thickness substantially thinner than the first layer W and the second layer B. Then quantum-wave interference layers and carrier accumulation layers are formed in series.
    Type: Grant
    Filed: May 26, 1999
    Date of Patent: April 22, 2003
    Assignee: Canare Electric Co., Ltd.
    Inventor: Hiroyuki Kano
  • Patent number: 6538265
    Abstract: A nitride compound semiconductor light-emitting device having a stack of layers including an active layer for a light emitting device and a method of manufacturing the device is disclosed. The method includes the steps of growing a first layer on a substrate at a first temperature to obtain an incomplete crystalline structure including both indium and aluminum and having the composition expressed as InXAlYGa1−X−YN (0≦X≦1, 0≦Y≦1). The method grows a cap layer on the first layer to cover the first layer, with growth of the cap layer proceeding at a second temperature substantially equal to or below the first temperature. The first layer is heat treated at a third temperature above the first temperature to cause the incomplete crystalline structure to crystallize and to create areas of differing compositions, thus changing the first layer to an active layer. The material of the cap layer is selected to be heat stable during the heat-treating step.
    Type: Grant
    Filed: September 13, 1999
    Date of Patent: March 25, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideto Sugawara
  • Patent number: 6515316
    Abstract: A HEMT device comprises a buffer layer disposed over a substrate. A partially-relaxed channel is disposed over the buffer layer and a barrier layer is disposed over the channel. A cap layer is disposed over the barrier layer and a gate is positioned on the barrier layer. A source and a drain are positioned on the barrier layer on opposite sides of the gate.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: February 4, 2003
    Assignee: TRW Inc.
    Inventors: Michael Wojtowicz, Tsung-Pei Chin, Michael E. Barsky, Ronald W. Grundbacher
  • Patent number: 6476412
    Abstract: A semiconductor device is constituted by a quantum-wave interference layer with plural periods of a pair of a first layer W and a second layer B. The second layer B has wider band gap than the first layer W. Each thickness of the first layer W and the second layer B is determined by multiplying by an odd number one fourth of wavelength of quantum-wave of carriers in each of the first layer W and the second layer B existing around the lowest energy level of the second layer B. A &dgr; layer, for sharply varying energy band, is formed at an every interface between the first layer W and the second layer B and has a thickness substantially thinner than the first layer W and the second layer B. The quantum-wave interference layer functions as a reflecting layer of carriers for higher reflectivity.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: November 5, 2002
    Assignee: Canare Electric Co., Ltd.
    Inventor: Hiroyuki Kano
  • Patent number: 6459103
    Abstract: An InP/InGaAlAs heterojunction bipolar transistor with the characteristics of amplification and negative-differential-resistance phenomenon is presented in the invention. The 3-terminal current-voltage characteristics of the heterojunction bipolar transistor can be controlled by the applied base current. In the large collector current regime, the heterojunction bipolar transistor has the characteristics as similar to conventional bipolar junction transistors. However, in a small collector current regime, both the transistor active region and negative-differential-resistance loci are observed. The negative-differential-resistance phenomenon is caused by the insertion of a thin base layer and a &dgr;-doped sheet. Moreover, the use of a setback layer with a thickness of 50 Å added at the emitter-base junction can suppress the diffusion of doping impurity in the base and reduce the potential spike at emitter-base heterojunction so as to improve the confinement of holes injected from base to emitter.
    Type: Grant
    Filed: January 26, 2000
    Date of Patent: October 1, 2002
    Assignee: National Science Council
    Inventors: Wen-Chau Liu, Wei-Chou Wang, Shiou-Ying Cheng
  • Patent number: 6382800
    Abstract: A light emitting semiconductor device, comprising: a GaAs substrate, a first semiconductor layer of AlzGa1−zAs (0<z≦1) or GatIn1−tPuAs1−u (0<t<1 and 0<u≦1), wherein the semiconductor layer has a band gap energy greater than that of GaAs, a spacer layer comprising at least one GaAs monolayer, wherein the spacer layer is formed on the semiconductor layer, and an active layer of GaxIn1−xNyAs1−y (0≦x ≦1 and 0<y<1) having a lattice strain not greater than 0.3% and lattice-matched with the GaAs substrate, wherein the active layer is formed on the spacer layer.
    Type: Grant
    Filed: March 23, 1998
    Date of Patent: May 7, 2002
    Assignee: Ricoh Company, Ltd.
    Inventor: Shunichi Sato
  • Patent number: 6369436
    Abstract: A solid-state wavelength demultiplexer comprising a plurality of photosensitive elements wherein each element has certain energy gap defined by the material composition. All photosensitive elements are grown on a common substrate where the first grown buffer layer, adjacent and near lattice matched to the first bottom photosensitive element, is heavily doped. A composition of photosensitive elements varies from the first bottom photosensitive element up to a first top photosensitive layer in such a way that corresponding energy gap has a minimum value in the lowermost element while the maximum value in the uppermost element. A wide gap doped “window” layer is grown on top of the uppermost element. Each individual photosensitive element consists of at least three sublayers comprising a first doped sublayer, a second heavily doped sublayer, and a photosensitive undoped sublayer sandwiched between them.
    Type: Grant
    Filed: May 22, 2000
    Date of Patent: April 9, 2002
    Inventor: Boris Gilman
  • Patent number: 6353238
    Abstract: A novel use of a solid state light detector with a low impedance substrate is described. Light that enters the substrate after traversing the antireflective layer creates an electron-hole pair. The electrons are collected in a crystalline epitaxial layer that spans the space charge region, or depletion layer. A high electric field accelerates free electrons inside the depletion region. The electrons collide with the lattice to free more holes and electrons resulting from the presence of a n-p junction, or diode. The diode is formed by placing the crystalline layer which has positive doping in close proximity with the electrodes which have negative doping. The continual generation of charge carriers results in avalanche multiplication with a large multiplication coefficient. During the avalanche process, electrons can be collected enabling light detection. A resistive layer is used to quench, or stop, the avalanche process.
    Type: Grant
    Filed: April 23, 2001
    Date of Patent: March 5, 2002
    Assignee: Board of Regents, The University of Texas System
    Inventors: Peter P. Antich, Edward N. Tsyganov
  • Patent number: 6337492
    Abstract: The light emitting device comprises a plurality of stacked organic light emitting devices. The plurality of organic light emitting devices are arranged in a stack. The light emitting device further includes a controller for controlling operation of each of the plurality of organic light emitting devices in the stack. The controller supplies the same current to each of the organic light emitting devices in the stack. The controller simultaneously supplies the same current to each of the plurality of the organic light emitting devices.
    Type: Grant
    Filed: May 8, 1998
    Date of Patent: January 8, 2002
    Assignee: eMagin Corporation
    Inventors: Gary W. Jones, Webster E. Howard
  • Patent number: 6337508
    Abstract: A transistor having an electron quantum-wave interference layer with plural periods of a pair of a first layer W and a second layer B in a p-layer of a pn junction structure. The second layer B has wider band gap than the first layer W. Each thicknesses of the first layer W and the second layer B is determined by multiplying by an odd number one fourth of quantum-wave wavelength of carriers in each of the first layer W and the second layer B, the carriers existing around the lowest energy level of the second layer B. The quantum-wave interference layer functions as an electron reflecting layer, and enables to lower a dynamic resistance of the transistor notably. An amplification factor of a bipolar transistor of an npn junction structure, having the electron reflecting layer is improved compared with a transistor without an electrode reflecting layer. Similarly, a transistor having a hole reflecting layer, which has a larger amplification factor, can be obtained.
    Type: Grant
    Filed: October 22, 1999
    Date of Patent: January 8, 2002
    Assignee: Canare Electric Co., Ltd.
    Inventor: Hiroyuki Kano
  • Patent number: 6331716
    Abstract: A variable capacity device having an nin, pip, nn−p, np−p, or nip junction whose middle layer is constituted by a quantum-wave interference layer with plural periods of a first layer W and a second layer B as a unit. The second layer B has a wider band gap than the first layer W. Each thickness of the first layer W and the second layer B is determined by multiplying by an odd number one fourth of a wavelength of a quantum-wave of carriers in each of the first layer W and the second layer B existing around the lowest energy level of the second layer B. A &dgr; layer, for changing energy band suddenly, is formed at interfaces between the first layer W and the second layer B and has a thickness substantially thinner than the first layer W and the second layer B. Plurality of quantum-wave interference units are formed sandwiching carrier accumulation layers in series. Then a voltage-variation rate of capacity of the variable capacity device is improved.
    Type: Grant
    Filed: February 5, 1999
    Date of Patent: December 18, 2001
    Assignee: Canare Electric Co., Ltd.
    Inventor: Hiroyuki Kano
  • Patent number: 6297516
    Abstract: A patterning system with a photoresist overhang allows material to be deposited onto a substrate in various positions by varying the angle from which the material is deposited, and by rotating the substrate. The patterning system can be used to fabricate a stack of organic light emitting devices on a substrate using the same patterning system and without removing the substrate from vacuum.
    Type: Grant
    Filed: June 25, 1999
    Date of Patent: October 2, 2001
    Assignee: The Trustees of Princeton University
    Inventors: Stephen R. Forrest, Vladimir Bulovic, Paul Burrows
  • Patent number: 6271537
    Abstract: Quantum-well sensors having an array of spatially separated quantum-well columns formed on a substrate. A grating can be formed increase the coupling efficiency.
    Type: Grant
    Filed: November 19, 1999
    Date of Patent: August 7, 2001
    Assignee: California Institute of Technology
    Inventors: Sarath D. Gunapala, Sumith V. Bandara, John K. Liu, Daniel W. Wilson
  • Patent number: 6255695
    Abstract: In a field-effect transistor, one of the distance between a gate electrode and a source electrode and the distance between the gate electrode and a drain electrode which one distance is on a side where a signal of a high frequency is applied is made longer than the other distance on a side where a signal of a low frequency is applied.
    Type: Grant
    Filed: September 18, 1997
    Date of Patent: July 3, 2001
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Yasushi Kubota, Kenichi Katoh, Jun Koyama
  • Patent number: 6246069
    Abstract: A thin-film edge field emitter device includes a substrate having a first portion and having a protuberance extending from the first portion, the protuberance defining at least one side-wall, the side-wall constituting a second portion. An emitter layer is disposed on the substrate including the second portion, the emitter layer being selected from the group consisting of semiconductors and conductors and is a thin-film including a portion extending beyond the second portion and defining an exposed emitter edge. A pair of supportive layers is disposed on opposite sides of the emitter layer, the pair of supportive layers each being selected from the group consisting of semiconductors and conductors and each having a higher work function than the emitter layer.
    Type: Grant
    Filed: April 20, 1998
    Date of Patent: June 12, 2001
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: David S. Hsu, Henry F. Gray
  • Patent number: 6242764
    Abstract: Disclosed is a GaN-based compound semiconductor light-emitting element, comprising an AlN buffer layer, a GaN lattice strain moderating layer, and an n-type AlGaN contact layer formed on the layer. The GaN lattice strain moderating layer has a lattice constant larger than that of the AlN buffer layer. On the other hand, the contact layer has a lattice constant smaller than that of the AlN buffer layer. Further, the GaN lattice strain moderating layer has a thickness falling within a range of between 0.01 &mgr;m to 0.5 &mgr;m.
    Type: Grant
    Filed: July 17, 1998
    Date of Patent: June 5, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuo Ohba, Hiroaki Yoshida