Abstract: Methods of manufacturing a photo diode include sequentially forming a buried layer of a first conductivity type, a first epitaxial layer of the first conductivity type, and a second epitaxial layer of a second conductivity type on a substrate. The second and first epitaxial layers are etched to form a trench that exposes a portion of the buried layer. A conductive plug of the first conductivity type is formed in the trench. A first electrode is formed on an upper surface of the second epitaxial layer. A second electrode may be formed to contact an upper surface of the conductive plug. Photodiodes having a conductive plug contact to a buried layer are also provided.

Abstract: In a metal gate replacement process, a gate electrode stack may be formed of a dielectric covered by a sacrificial metal layer covered by a polysilicon gate electrode. In subsequent processing of the source/drains, high temperature steps may be utilized. The sacrificial metal layer prevents reactions between the polysilicon gate electrode and the underlying high dielectric constant dielectric. As a result, adverse consequences of the reaction between the polysilicon and the high dielectric constant dielectric material can be reduced.

Abstract: A method for forming a trench capacitor is presented in the following process steps. A trench is formed on a semiconductor substrate. A first trench dielectric is deposited into the trench without reaching a full height thereof. An etch stop layer is formed on the first trench dielectric and along inner surfaces of the trench. A second trench dielectric is deposited on the etch stop layer. The second trench dielectric and the etch stop layer are removed to expose the first trench dielectric in the trench. A conductive layer is formed on the first trench dielectric in the trench, such that the conductive layer, the first trench dielectric and the semiconductor substrate function as a trench capacitor.

Abstract: The present application provides a semiconductor device including a first-conductivity type semiconductor substrate, a pillar structure portion formed on the first-conductivity type semiconductor substrate and formed of five semiconductor pillar layers arranged in one direction parallel to a main surface of the first-conductivity type semiconductor substrate, and isolation insulating portions formed on the first-conductivity type semiconductor substrate and sandwiching the pillar structure portion between the isolation insulating portions, wherein the pillar structure portion is formed of a first first-conductivity type pillar layer, a second first-conductivity type pillar layer and a third first-conductivity type pillar layer which sandwich the first first-conductivity type pillar layer, a first second-conductivity type pillar layer provided between the first first-conductivity type pillar layer and the second first-conductivity type pillar layer, and a second second-conductivity type pillar layer provided b

Abstract: A method of fabricating an organic optoelectronic device having a bulk heterojunction comprises the steps of: depositing a first layer over a first electrode by organic vapor phase deposition, wherein the first layer comprises a first organic small molecule material; depositing a second layer on the first layer such that the second layer is in physical contact with the first layer, wherein the interface of the second layer on the first layer forms a bulk heterojunction; and depositing a second electrode over the second layer to form the optoelectronic device. In another embodiment, a first layer having protrusions is deposited over the first electrode, wherein the first layer comprises a first organic small molecule material. For example, when the first layer is an electron donor layer, the first electrode is an anode, the second layer is an electron acceptor layer, and the second electrode is a cathode.

Abstract: The present invention provides a method for producing thin nickel (Ni) monosilicide or NiSi films (having a thickness on the order of about 30 nm or less), as contacts in CMOS devices wherein an amorphous Ni alloy silicide layer is formed during annealing which eliminates (i.e., completely by-passing) the formation of metal-rich silicide layers. By eliminating the formation of the metal-rich silicide layers, the resultant NiSi film formed has improved surface roughness as compared to a NiSi film formed from a metal-rich silicide phase. The method of the present invention also forms Ni monosilicide films without experiencing any dependence of the dopant type concentration within the Si-containing substrate that exists with the prior art NiSi films.

Abstract: Polymers are described which exhibit a resistive hysteresis effect. The polymers include a polymer backbone to which pentaarylcyclopentadienyl radicals are bonded as side groups. A resistive memory element is formed that includes the polymer as a storage medium. By applying a voltage, the memory element can be switched between a nonconductive and a conductive state.

Abstract: A method of fabricating a vertical MIM capacitor. An insulation layer is formed on the substrate. The insulation layer is patterned to form an opening in a predetermined area of a core electrode. Then, the opening is filled to form a sacrificial plug. Subsequently, the insulation layer is patterned to form a trench in a predetermined area of an outer electrode around the sacrificial plug. A fenced insulation layer is formed around the sacrificial plug simultaneously. After the sacrificial plug is removed, a metal layer is filled in the predetermined area of the core and outer electrodes. A vertical MIM capacitor comprising the core electrode, the fenced insulation layer, and the outer electrode is finally formed. The invention also provides a vertical MIM capacitor.

Abstract: A III-nitride power semiconductor device that includes a heterojunction body with a sloping portion, a first power electrode, a second power electrode and a gate over the sloping portion of the heterojunction to control the conduction of current between the first power electrode and the second power electrode of the HI-nitride power semiconductor device.

Abstract: A method of forming a metal line in a semiconductor device using a fluorine doped silica glass (FSG) insulation layer. The method includes forming a lower metal layer on a insulation layer on a semiconductor substrate, forming a metal oxide layer on a sidewall of the lower metal layer, forming a barrier insulation layer covering the lower metal layer and metal oxide layer, forming an FSG insulation layer on the barrier insulation layer, forming a via contact that penetrates the FSG insulation layer so as to connect to the lower metal layer, and forming an upper metal layer electrically connected to the via contact.

Abstract: A microsensor fabricated with a ferroelectric material and a fabrication method therefor are provided. The microsensor includes a support, an insulating layer on the support, a first electrode on the insulating layer, a ferroelectric layer having at least a metal on the insulating layer and the first electrode, and at least a second electrode on the ferroelectric layer.

Abstract: Two ferroelectric capacitors including a PZT film are connected to one MOS transistor. Electrodes of the ferroelectric capacitor are arranged above a main plane of a substrate parallel to the main plane. Therefore, high capacity can be obtained easily. Furthermore, a (001) direction of the PZT film is parallel to the virtual straight line linking between the two electrodes. Therefore, a direction in which an electric field is applied coincides with a direction of a polarization axis, so that high electric charge amount of remanent polarization can be obtained.

Abstract: A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.

Abstract: In a method of manufacturing a semiconductor device such as a flash memory device, an insulating pattern having an opening is formed to partially expose a surface of a substrate. A first silicon layer is formed on the exposed surface portion of the substrate and the insulating pattern. The first silicon layer has an opened seam overlying the previously exposed portion of the substrate. A heat treatment on the substrate is performed at a temperature sufficient to induce silicon migration so as to cause the opened seam to be closed via the silicon migration. A second silicon layer is then formed on the first silicon layer. Thus, surface profile of a floating gate electrode obtained from the first and second silicon layers may be improved.

Abstract: A method of forming a semiconductor device uses an anneal technique to planarize and round corners of a trench formed in a substrate. The substrate is annealed under a normal pressure in an inert atmosphere, such as an atmosphere containing one of argon, helium, and neon, or an atmosphere of a gas mixture of hydrogen of 4% or less and one of argon, helium, and neon at a temperature of between 900° C. and 1050° C. for a time of between 30 seconds and 30 minutes to round the trench corners and planarize the trench side walls. Alternatively, after removing a mask for forming the trench, the substrate can be annealed in the inert atmosphere. This provides easy and inexpensive way of planarizing the trench side walls, as well as rounding of the trench corners. Moreover, by removing the mask for forming the trench before annealing enables the semiconductor device to have a highly reliable gate insulator film with good reproducibility.

Abstract: A method for fabricating a thin film pattern on a substrate, includes the steps of: forming a concave part on the substrate that conforms to the thin film pattern; and applying a function liquid into the concave part.

Abstract: Stress is exerted to the SiC crystal in the region, in which the carriers of a SiC semiconductor device flow, to change the crystal lattice intervals of the SiC crystal. Since the degeneration of the conduction bands in the bottoms thereof is dissolved, since the inter-band scattering is prevented from causing, and since the effective electron mass is reduced due to the crystal lattice interval change, the carrier mobility in the SiC crystal is improved, the resistance of the SiC crystal is reduced and, therefore, the on-resistance of the SiC semiconductor device is reduced.

Abstract: An organic semiconductor material characterized by having a structure represented by chemical formula 1, the planarity of a main chain A1-X-A2 being disintegrated by steric hindrance between B1 and X and steric hindrance between B2 and X, the organic semiconductor material having a number average molecular weight of about 2,000 to about 200,000: wherein A1, A2, B1, B2 and X each have a skeleton structure comprising L 6 ? electron rings, M 8 ? electron rings, N 10 ? electron rings, O 12 ? electron rings, P 14 ? electron rings, Q 16 ? electron rings, R 18 ? electron rings, S 20 ? electron rings, T 22 ? electron rings, U 24 ? electron rings, and V 26 ? electron rings, wherein L, M, N, O, P, Q, R, S, T, U, and V are each an integer of 0 (zero) to 6 and L+M+N+O+P+Q+R+S+T+U+V=1 to 6; and B1 and B2 have an alkyl group.

Abstract: Embodiments of the present invention provide a method of fabricating a contact structure in a layer of dielectric material between a semiconductor device and a back-end-of-line interconnect. The method includes creating at least one contact opening in said layer of dielectric material; forming a first TiN film through a chemical-vapor deposition process, said first TiN film lining said contact opening; and forming a second TiN film through a physical vapor deposition process, said second TiN film lining said first TiN film. A contact structure fabricated according to embodiments of the invention is also provided.

Abstract: A contact plug structure for a checkerboard dynamic random access memory comprises a body portion, two leg portions connected to the body portion and a dielectric block positioned between the two leg portions. Each leg portion is electrically connected to a deep trench capacitor arranged in an S-shape manner with respect to the contact plug structure via a doped region isolated by a shallow trench isolation structure. Preferably, the body portion and the two leg portions can be made of the same conductive material selected from the group consisting of polysilicon, doped polysilicon, tungsten, copper and aluminum, while the dielectric block can be made of material selected from the group consisting of borophosphosilicate glass. Particularly, the contact plug can be prepared by dual-damascene technique. Since the overlapped area between the contact plug structure and a word line can be dramatically decreased, the bit line coupling (BLC) can be effectively reduced.