Abstract: There is provided a substrate processing method and apparatus which can measure and monitor thickness and/or properties of a film formed on a substrate as needed, and quickly correct a deviation in process conditions, and which can therefore stably provide a product of constant quality. A substrate processing method for processing a substrate having a metal and an insulating material exposed on its surface in such a manner that a film thickness of the metal, with an exposed surface of the metal as a reference plane, is selectively or preferentially changed, including measuring a change in the film thickness and/or a film property of the metal during and/or immediately after processing, and monitoring processing and adjusting processing conditions based on results of this measurement.

Abstract: A plasma doping method that can control a dose precisely is realized. In-plane uniformity of the dose is improved. It has been found that, if a bias is applied by irradiating B2H6/He plasma onto a silicon substrate, there is a time at which a dose of boron is made substantially uniform, and the saturation time is comparatively long and ease to stably use, compared with a time at which repeatability of an apparatus control can be secured. The invention has been finalized focusing on the result. That is, if plasma irradiation starts, a dose is initially increased, but a time at which the dose is made substantially uniform without depending on a time variation is continued. In addition, if the time is further increased, the dose is decreased. The dose can be accurately controlled through a process window of the time at which the dose is made substantially uniform without depending on the time variation.

Abstract: Provided is a manufacturing method of a nitride semiconductor device having a nitride semiconductor substrate (e.g. GaN substrate) in which dislocation concentrated regions align in stripe formation, the dislocation concentrated regions extending from a front surface to a back surface of the substrate, the manufacturing method being for stacking each of a plurality of nitride semiconductor layers on the front surface of the substrate in a constant film thickness. Grooves are formed on the nitride semiconductor substrate in the immediate areas of dislocation concentrated regions. Each of the nitride semiconductor layers is formed as a crystal growth layer on the main surface of the nitride semiconductor substrate to which the grooves have been formed.

Abstract: An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.

Abstract: A thin film transistor array substrate and a fabricating method for simplifying a process and reducing a manufacturing cost. In the thin film transistor array substrate, a gate line is formed on a substrate and a gate insulating film is formed on the gate line. A data line is provided in such a manner to intersect the gate line with having the gate insulating film therebetween, and contains any at least one of tungsten silicide (WSix), cobalt silicide (CoSix) and nickel silicide (NiSix). A thin film transistor is provided at each intersection between the gate line and the data line. A pixel electrode is provided at a pixel area defined by each intersection between the gate line and the data line and is connected to the thin film transistor.

Abstract: A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The unit cell includes a MESFET having a source, a drain and a gate. The gate is between the source and the drain and on a channel layer of the MESFET. The channel layer has a first thickness on a source side of the channel layer and a second thickness, thicker than the first thickness, on a drain side of the channel layer. Related methods of fabricating MESFETs are also provided herein.

Abstract: A semiconductor structure having an efficient thermal path and a method for forming the same are provided. The semiconductor structure includes a protection ring over a semiconductor substrate and substantially encloses a laser fuse structure. The laser fuse structure includes a laser fuse and a connection structure connecting the fuse to integrated circuits. The protection ring is thermally coupled to the semiconductor substrate by contacts. The semiconductor structure further includes a metal plate conducting heat generated by a laser beam to the protection ring.

Abstract: Methods of forming a metal oxide surface that is enriched with metal oxide in its higher oxidation state are provided. A metal oxide surface that is enriched with metal oxide in its higher oxidation state is also provided.

Abstract: A structure and method of fabricating a high-mobility semiconductor layer structure and field-effect transistor (MODFET) that includes a high-mobility conducting channel, while at the same time, maintaining counter doping to control deleterious short-channel effects. The MODFET design includes a high-mobility conducting channel layer wherein the method allows the counter doping to be formed using a standard technique such as ion implantation, and further allows the high-mobility channel to be in close proximity to the counter doping without degradation of the mobility.

Abstract: Provided is a field effect transistor having an organic semiconductor layer, in which the organic semiconductor layer contains at least a tetrabenzo copper porphyrin crystal and has peaks at two or more of Bragg angles (2?) in CuK? X-ray diffraction of 8.4°±0.2°, 10.2°±0.2°, 11.8°±0.2°, and 16.9°±0.2°, and the tetrabenzo copper porphyrin crystal comprises a compound represented by the following general formula (1). (Wherein R2's each represent a hydrogen atom, a halogen atom, a hydroxyl group, or an alkyl group, oxyalkyl group, thioalkyl group, or alkylester group having 1 to 12 carbon atoms, and R3's each represent a hydrogen atom or an aryl group.).

Abstract: A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.

Abstract: Novel silylethynylated heteroacenes and electronic devices made with those compounds are disclosed.

Abstract: The present invention is directed towards processes for covalently attaching molecular wires and molecular electronic devices to carbon nanotubes and compositions thereof. Such processes utilize diazonium chemistry to bring about this marriage of wire-like nanotubes with molecular wires and molecular electronic devices.

Abstract: A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and forming a non-strained device in the relaxed material is disclosed. In one embodiment, the strained material is silicon (Si) in either a tensile or compressive state, and the relaxed material is Si in a normal state. A buffer layer of silicon germanium (SiGe), silicon carbon (SiC), or similar material is formed on the substrate and has a lattice constant/structure mis-match with the substrate. A relaxed layer of SiGe, SiC, or similar material is formed on the buffer layer and places the strained material in the tensile or compressive state. In another embodiment, carbon-doped silicon or germanium-doped silicon is used to form the strained material. The structure includes a multi-layered substrate having strained and non-strained materials patterned thereon.

Abstract: The specification describes a multi-chip module (MCM) that contains an integrated passive device (IPD) as the carrier substrate (IPD MCM). Parasitic electrical interactions are controlled at one or both interfaces of the IPD either by eliminating metal from the interfaces, or by selective use of metal in parts of the MCM that are remote from the sensitive device components. The sensitive device components are primarily analog circuit components, especially RF inductor elements. In the IPD layout, the sensitive components are segregated from other components. This allows implementation of the selective metal approach. It also allows parasitic interactions on top of the IPD substrate to be reduced by selective placement of IC semiconductor chips and IC chip ground planes. In preferred embodiments of the IPD MCM of the invention, the IPD substrate is polysilicon, to further minimize RF interactions. The various methods of assembling the module may be adapted to keep the overall thickness within 1.0 mm.

Abstract: An organic electroluminescent device includes: first and second substrates facing each other and spaced apart from each other, the first and second substrates having a central portion and a peripheral portion; an array layer on the first substrate, the array layer including a thin film transistor; an organic electroluminescent diode on the second substrate; a connection pattern between the first and second substrates, the connection pattern electrically connecting the thin film transistor and the organic electroluminescent diode; and a seal pattern in the peripheral portion, the seal pattern including a metallic material for attaching the first and second substrates.

Abstract: A method for batch manufacturing of slabs for zig-zag lasers including steps of bonding two non-active media to either side of an active medium to form a sandwich, dicing the sandwich to provide slices, rendering two surfaces of each slice into total-internal-reflection (TIR) surfaces, and then dicing the slices perpendicular to the TIR surfaces to provide a plurality of zig-zag slabs.

Abstract: A SiGe bipolar transistor including a semiconductor substrate having a collector and sub-collector region formed therein, wherein the collector and sub-collector are formed between isolation regions that are also present in the substrate is provided. Each isolation region includes a recessed surface and a non-recessed surface which are formed utilizing lithography and etching. A SiGe layer is formed on the substrate as well as the recessed non-recessed surfaces of each isolation region, the SiGe layer includes polycrystalline Si regions and a SiGe base region. A patterned insulator layer is formed on the SiGe base region; and an emitter is formed on the patterned insulator layer and in contact with the SiGe base region through an emitter window opening.

Abstract: A Double Heterojunction Bipolar Transistor (DHBT) is disclosed employing a collector of InP, an emitter of InP or other material such as InAlAs, and a base of either a selected InxGa1−xAsySb1−y compound, which preferably is lattice-matched to InP or may be somewhat compressively strained thereto, or of a superlattice which mimics the selected InGaAsSb compound. When an emitter having a conduction band non-aligned with that of the base is used, such as InAlAs, the base-emitter junction is preferably graded using either continuous or stepped changes in bulk material, or using a chirped superlattice. Doping of the junction may include one or more delta doping layer to improve the shift of conduction band discontinuities provided by a grading layer, or to permit a wider depletion region.

Abstract: A single-electron transistor includes a projecting feature, such as a pyramid, that projects from a face of a substrate. A first electrode is provided on the substrate face that extends onto the projecting feature. A second electrode is provided on the substrate face that extends onto the projecting feature and that is spaced apart from the first electrode. At least one nanoparticle is provided on the projecting feature between the first and second electrodes. Accordingly, the geometric configuration of the projecting feature can define the spacing between the first and second electrodes.