Abstract: A pressure sensor having a flexible membrane which is moved by an external force, such as pressure from an air flow. The flexible membrane extends over a semiconductor frame having an opening, such that a portion of the flexible membrane extends over the semiconductor frame, and a portion of the flexible membrane extends over the opening. An inherent tensile stress is present in the membrane. One or more strain gage resistors are formed on the portion of the membrane which extends over the opening of the semiconductor frame. The membrane deforms in response to an externally applied pressure. As the membrane deforms, the strain gage resistors elongate, thereby increasing the resistances of these resistors. This change in resistance is measured and used to determine the magnitude of the external pressure. In one embodiment, a Wheatstone bridge circuit is used to translate the change in resistance of the strain gage resistors into a differential voltage.

Abstract: A high performance single package multi-chip module multiplies the logic density of the highest density monolithic programmable logic device (PLD). A dual-sided substrate carries multiple prepackaged PLDs on a top side and a field programmable interconnect (FPIC) die on a bottom side. The prepackaged PLDs and the ability to use the substrate as a burn-in vehicle for the FPIC die results in reliable and reworkable assembly process with minimized yield loss.

Abstract: A method for manufacturing a semiconductor device such as a thin film transistor using a crystal silicon film is provided. The crystal silicon film is obtained by selectively forming films, particles or clusters containing nickel, iron, cobalt, ruthenium, rhodium, paradium, osmium, iridium, platinum, scandium, titanium, vanadium, chrome, manganese, copper, zinc, gold, silver or silicide thereof in a form of island, line, stripe, dot or film on or under an amorphous silicon film and using them as a starting point, by advancing its crystallization by annealing at a temperature lower than a normal crystallization temperature of an amorphous silicon. A transistor whose leak current is low and a transistor in which a mobility is high are obtained in the same time in structuring a dynamic circuit having a thin film transistor by selectively forming a cover film on a semiconductor layer which is to become an active layer of the transistor and by thermally crystallizing it thereafter.

Abstract: An insulated gate field effect transistor is constructed by first forming a non-single crystalline semiconductor layer or island on an insulating surface of a substrate. A gate insulating layer is then formed on the semiconductor layer. A gate electrode is formed on the gate insulating layer. An impurity is added to a portion of the semiconductor layer to form source and drain regions, and the semiconductor layer is irradiated with light through the gate insulating layer. In preferred embodiments, the substrate is maintained at a temperature less than 400° C. and the light have a wavelength of 250-600 nm.

Abstract: The invention relates to a high-capacitance capacitor which is monolithically integratable on a semiconductor substrate doped with a first type of dopant and accommodating a diffusion well which is doped with a second type of dopant and has a first active region formed therein. A layer of gate oxide is deposited over the diffusion well which is covered with a first layer of polycrystalline silicon and separated from a second layer of polycrystalline silicon by an interpoly dielectric layer. Advantageously, the high-capacitance capacitor of the invention includes a first elementary capacitor having the first and second layers of polycrystalline silicon as its conductive plates, and the interpoly dielectric layer as the isolation dielectric, and a second elementary capacitor having the first layer of polycrystalline silicon and the diffusion well as its conductive plates and the gate oxide layer as the isolation dielectric.

Abstract: A method for fabricating an integrated circuit transistor begins with doping the substrate in the device active areas after field oxide regions have been formed. This dopant helps to reduce short channel transistor effects. A thin layer of epitaxial silicon is then grown over the substrate active regions. A field effect transistor is formed in the epitaxial layer and underlying substrate. The transistor channel region is in the relatively lightly doped epitaxial layer, but the underlying doped substrate layer helps minimize short channel effects.

Abstract: A method for fabricating a compound semiconductor device includes the steps of depositing a first group III-V compound semiconductor layer on a surface of a Si substrate while holding a temperature of the Si substrate at a first temperature, depositing a second group III-V compound semiconductor layer on the first group III-V compound semiconductor layer while holding the temperature of the substrate at a second, higher temperature, and depositing a third group III-V compound semiconductor layer on the second group III-V compound semiconductor layer while holding the temperature of the substrate at a third temperature higher than said second temperature, wherein the second group III-V compound semiconductor layer contains Al.

Abstract: To fabricate back side contact pads that are suitable for use in a vertical integrated circuit, vias are made in the face side of a wafer, and dielectric and contact pad metal are deposited into the vias. Then the wafer back side is etched until the metal is exposed. When the etch exposes the insulator at the via bottoms, the insulator is etched slower than the wafer material (e.g. silicon). Therefore, when the dielectric is etched off and the metal is exposed, the dielectric protrudes down from the wafer back side around the exposed metal contact pads, by about 8 &mgr;m in some embodiments. The protruding dielectric portions improve insulation between the wafer and the contact pads when the contact pads are soldered to an underlying circuit. In some embodiments, before the contact pads are soldered, additional dielectric is grown on the wafer back side without covering the contact pads.

Abstract: Concentration of metal element which promotes crystallization of silicon and which exists within a crystalline silicon film obtained by utilizing the metal element is reduced. A first heat treatment for crystallization is performed after introducing nickel to an amorphous silicon film 103. Then, laser light is irradiated to diffuse nickel element which is concentrated locally. After that, another heat treatment is performed within an oxidizing atmosphere at a temperature higher than that of the previous heat treatment. At this time, HCl or the like is added to the atmosphere. A thermal oxide film 106 is formed in this step. At this time, gettering of the nickel element into the thermal oxide film 106 takes place. Then, the thermal oxide film 106 is removed. Thereby, a crystalline silicon film 107 having low concentration of the metal element and a high crystallinity can be obtained.

Abstract: A manufacturing system for a semiconductor device manages a lower pattern (100) corresponding to a pattern (200) in the semiconductor device and the rotation of the lower pattern (100) from the position of a reference axis ±0 to the position of a central axis of the pattern (100). The manufacturing system generates a stepper correction value including the rotation of the lower pattern (100) to determine the position of the pattern (200) and gives the stepper correction value to a stepper. With the stepper correction value, it is possible to prevent any shear out of specification between the upper and lower patterns. Thus, a method for correcting alignment and a method for manufacturing a semiconductor device, by which any shear is prevented, can be provided.

Abstract: A method of forming a multilayered pattern in an electronic part wherein a pattern of multilayer wiring is formed via insulating layers in which a pattern for a succeeding layer is formed by adjusting to a position and a configuration of the pattern which was already formed by recognizing a position and configuration of the pattern.

Abstract: A semiconductor device is formed having a low voltage transistor in a logic core portion and a high voltage transistor in an input/output portion. The low voltage transistor is formed by ion implanting nitrogen into the surface and forming a gate oxide layer on the nitrogen implanted surface portion of the semiconductor substrate in the logic core region. The implanted nitrogen retards the growth of the gate oxide layer in the nitrogen implanted area, thereby enabling formation of gate oxide layers having different thicknesses.

Abstract: A silicon film provided on a blocking film 102 on a substrate 101 is made amorphous by doping Si+, and in a heat-annealing process, crystallization is started in parallel to a substrate from an an 100 where lead serving as a crystallization-promoting catalyst is introduced.

Abstract: Improved multilayer matrix line including inverted gate thin film matrix transistors to reduce defects in and enhance performance of matrix devices incorporating the transistors, including active matrix displays. The inverted gate line is formed in a multilayer metal structure deposited sequentially before patterning of a first bottom refractory layer, an aluminum layer and a second refractory layer for the gate structure. The aluminum layer is anodized adjacent the gate to prevent step coverage problems. A further improvement is provided when forming an active matrix display storage capacitor utilizing the multilayer gate structure.

Abstract: A process for providing precision deposits (3) of metal films unto a working substrate (5) by transmitting an ultrafast laser pulse thorough a transparent target substrate (6) whose lower surface supports a metal film (7). Rapid laser heating produces pressure that propels vaporized metal unto the working substrate whereupon the metal vapor rapidly resolidifies on a dimension substantially equal to the ultrafast laser's focal spot size.

Abstract: A first substrate of the three layer structure composed of a lower layer portion consisting of silicon, a middle layer portion consisting of SiO.sub.2 and an upper layer portion consisting of silicon is prepared. Impurity is doped into the lower layer portion so that it has conductivity. The lower surface of the lower layer portion is etched to form a diaphragm portion and a pedestal portion, and then a second substrate consisting of glass is joined to the portion therebelow. By the electrodes on the second substrate and the diaphragm portion, capacitance elements are formed. Grooves are dug by a dicing blade from the upper surface of the upper layer portion thereafter to downwardly dig the bottom portions of the grooves by etching until the upper surface of the lower layer portion is exposed. When the respective unit areas are cut off, there is obtained a structure in which a weight body is positioned at the central portion of the diaphragm portion and a pedestal is formed at the periphery thereof.

Abstract: A process for manufacturing an integrated circuit provides for the formation of a matrix of floating-gate non-volatile memory cells having dual polysilicon levels, with the two polysilicon levels being isolated by a gate dielectric layer (4) and an interpoly dielectric layer (9) therebetween, and for the concurrent formation of one type of thick-oxide transistor (21) having an active area (7) in regions peripheral to the matrix. The process of the invention provides for removal, during the step of defining the first-level polysilicon (5), the polysilicon (5) from the active area (7) of the thick-oxide transistor (21), so that the gate oxide of the transistor (21) results from the superposition of the first (4) and second (9) dielectric layers.

Abstract: A laminated layer having a layer containing Al (In) and a layer not containing Al (In) alternately laminated one upon another is plasma etched by an etchant gas which can etch both the layers containing and not containing Al (In). An additive gas containing F is added to the etchant gas while a layer not containing Al (In) is etched. When the surface of the layer containing Al (In) is exposed, fluorides are formed on the surface of the layer containing Al (In) and the etching is automatically stopped. An emission peak specific to Al (In) is monitored to detect which layer is presently etched.

Abstract: A method for forming a capacitor of a semiconductor device. A lower electrode is prebaked before a dielectric layer is formed on the lower electrode. As a result, moisture or contaminants are removed from the lower electrode, increasing adhesion between the lower electrode and the dielectric layer formed on the lower electrode, thereby preventing the dielectric layer from being lifted and cracked due to inferior coating properties.

Abstract: A dielectric thin-film material for microwave applications, including use as a capacitor, the thin-film comprising a composition of barium strontium calcium and titanium of perovskite type (Ba.sub.x Sr.sub.y Ca.sub.1-x-y)TiO.sub.3. Also provided is a method for making a dielectric thin film of that formula over a wide compositional range through a single deposition process.