Abstract: A fabricating method of a capacitor includes two gates and a commonly used source/drain region formed on a substrate. Then, a process of sell align contact has been applied to make a pitted self align contact window (PSACW) to partly expose the commonly used source/drain region. Then an glue/barrier layer and a lower electrode of the capacitor are formed over the PSACW. Then a dielectric thin film with a material having high dielectric constant is formed over the lower electrode. Then, an upper electrode is formed over the dielectric thin film to complete a capacitor, which has a structure of metal insulator metal with a shape like the PSACW.

Abstract: The invention relates to a process for making a lateral PNP bipolar electronic device integrated monolithically on a semiconductor substrate together with other bipolar devices of the NPN type, said device being incorporated to an electrically insulated multilayer structure. The device includes a semiconductor substrate doped with impurities of the P type; a first buried layer doped with impurities of the N type to form a base region; and a second layer, overlying the first and having conductivity of the N type, to form an active area with opposite collector and emitter regions being formed in said active area and separated by a base channel region. The width of the base channel region is defined essentially by a contact opening formed above an oxide layer deposited over the base channel region. Advantageously, the contact opening is formed by shifting an emitter mask.

Abstract: The monolithic inductor (30) includes a substrate (38), a spiral metal trace (32) disposed insulatively above the substrate (38), where a parasitic capacitance (56) is generated between the spiral metal trace (32) and the substrate (38), and a depletion layer is generated under the spiral metal trace (32) with a depletion junction capacitance (58) coupled in series with the parasitic capacitance (56). The overall capacitance is thus reduced, which enhances the self-resonance frequency of the inductor (30). For the same self-resonance frequency, a thicker metal trace may be used to implement the inductor, resulting in an improved quality factor, Q.

Abstract: A method for producing a low-impedance contact between a metallizing layer and a semiconductor material and a method for producing a capacitor. The two methods are adapted to one another such that in the course of a single process, both contacts and capacitors can be formed. In particular, by the methods of the invention, the insulation layer, which forms when the first dopant for the contact is forced inward, can be used as a capacitance dielectric of a capacitor.

Abstract: A field effect transistor (30) has an array of transistors (31) made up of bonding pads (45-47) and sub-arrays of transistors (41-43). The bonding pads (45-47) are distributed between the sub-arrays of transistors (41-43) to reduce the maximum temperature that any portion of the FET (30) is exposed to while the FET (30) is in a conducting state. A similar effect can be appreciated by adjusting the threshold voltage or pinch-off resistance of the transistors in a portion (101) of an array of transistors (95).

Abstract: A high voltage DENMOS transistor (10) having improved ESD protection. The transistor (10) is optimized to provide maximum substrate current in order to turn on the inherent lateral npn transistor during an ESD event so that the lateral npn can dissipate the ESD event without damage to the transistor (10). This is accomplished by optimizing the overlap (A) of the drain extended region (16) and the gate electrode (28) to control the gate coupling to achieve maximum substrate current.

Abstract: A method for manufacturing a semiconductor, comprising crystallizing an amorphous silicon film formed on a substrate by employing lateral growth method using a catalyst element which accelerates the crystallization, wherein the duration of annealing accounts for 90% or more but less than 100% of the time for crystallization of the amorphous silicon film under the condition that no catalyst element is used.

Abstract: A semiconductor apparatus having at least a compound film containing nitrogen and a method for production of the same, wherein the compound film containing nitrogen is formed under conditions where the ratio of the flow rates of the nitrogen with respect to an inert gas is 0.125 to 1.0.

Abstract: A method of creating a layer-to-layer alignment mark in a semiconductor wafer includes the step of depositing a first conductor layer on a substrate associated with the semiconductor wafer. The method also includes the step of fabricating a number of alignment trenches in the first conductor layer. Moreover, the method includes the step of depositing a first insulator layer on the first conductor layer so as to fill the number of alignment trenches. Yet further, the method includes the step of removing material associated with the first insulator layer from the number of alignment trenches such that an upper surface of the first conductor layer and an upper surface of the first insulator layer define a first alignment step feature which possesses a predetermined height. The method also includes the step of depositing a second conductor layer on the semiconductor wafer subsequent to the removing step. A semiconductor wafer is also disclosed.

Abstract: An amorphous silicon film formed on the surface of a substrate is subjected to a laser annealing process in which the silicon film 30 is irradiated by a line-shaped laser beam having an irradiation area extending a greater length in a X direction and having an optical power profile with a half-width in a Y direction smaller than a pixel pitch in the Y direction. The line-shaped laser beam is fixed and the substrate on a stage is moved in the Y direction in such a manner that when the line-shaped laser beam strikes an area of an active matrix section in which a TFT is formed, the stage is moved at a low speed, while the stage is moved at a high speed when the line-shaped laser beam strikes other areas which do not require irradiation. As for an area in areas which a data driver section including TFTs arranged in a complicated fashion will be formed, the entire area is irradiated by the laser beam.

Abstract: An improved low-voltage MOS device having high ruggedness, low on-resistance, and improved body diode reverse recovery characteristics comprises a semiconductor substrate on which is disposed a doped upper layer of a first conduction type. The upper layer includes at its upper surface a blanket implant of the first conduction type, a heavily doped source region of the first conduction type, and a heavily doped body region of a second and opposite conduction type. The upper layer further includes a doped first well region of the first conduction type and a doped well region of the second conduction type underlying the source and body regions. The first well region underlies the second well region and merges with the blanket implant to form a heavily doped neck region that abuts the second well region at the upper surface of the upper layer. A gate comprising a conductive material separated from the upper layer by an insulating layer is disposed on the upper layer overlying the heavily doped neck region.

Abstract: Surface area of a semiconductor integrated circuit memory required by programmable fuse boxes is reduced, and the capacitive loading of a column address bus from the programmable fuse boxes is reduced by reducing the number of programmable boxes. Each programmable fuse box is connected through fuses to a plurality of redundant columns in memory arrays whereby any one or more of the redundant column lines can be addressed through the programmed fuse box in replacing a defective column line. An unprogrammed redundant column select line is connected to ground through the fuses connecting the unselected redundant column select lines to ground so that unprogrammed redundant columns are inactive.

Abstract: The integrated micromechanical sensor device contains a body with a substrate (1) on which an insulating layer (2) and thereon a monocrystalline silicon layer (3) are arranged, in which the silicon layer has trenches as far as the surface of the insulating layer, and the side walls of the trenches as well as the side of the silicon layer adjacent to the insulating layer have a first doping type (n.sup.+) and the silicon layer has a second doping type (n.sup.-) at least in a partial region of its remaining surface, in which the silicon layer has a transistor arrangement in a first region (TB) and a sensor arrangement in a second region (SB), for which the insulating layer (2) is partly removed under the second region. Such a sensor device has considerable advantages over known devices with regard to its properties and its production process.

Abstract: A measurement window 29 is set in a bump formation position found from the bump formation co-ordinates of bonding data in respect of an image that has been picked up of the external appearance of a stud bump 23 at an inspection position. The image in this measurement window 29 is converted to respective binary images based on binary conversion levels which are respectively individually set for measurement of bump pedestal 24 and for bump head 27. Of image grains constituted by continuous areas of the same image level in the binary image, an image grain having maximum area is extracted and the position, shape and dimensions of the bump pedestal 24 and bump head 27 are then respectively measured using respectively a hole-filled image and the hole portion of this extracted image grain. The quality and presence of a stud bump 23 are determined by comparing the measured values with set values.

Abstract: A method of fabricating a lower electrode of a capacitor. A sacrificial multilayer is formed on a semiconductor layer. The sacrificial multi-layer is a stack of alternating first and second sacrificial layers. A patterned first mask layer having a first opening above a conductive plug in the semiconductor substrate is formed on the sacrificial multi-layer. A planar spacer is formed on the sidewall of the first opening. A second mask layer is formed to fill the first opening. The planar spacer and the sacrificial multi-layer thereunder are anisotropically etched until the semiconductor substrate is exposed to form a second opening while using the first mask layer and second mask layer as a mask. The first sacrificial layers exposed by the second opening are isotropically etched to form a plurality of recesses. The second opening and the recesses are filled with a conductive material layer. Finally, the first mask layer, second mask layer, and sacrificial multi-layer are removed.

Abstract: An integrated circuit chip which has a volatile memory also has a non-volatile memory for storing the parameter of a volatile memory which was measured while the chip was part of a completed wafer.

Abstract: The microbridge structure comprises a substrate layer provided with two first electrical contacts, a microstructure provided with two second electrical contacts, and a micro support for suspending the microstructure over and at a predetermined distance from the substrate layer. The micro support extends along a vertical axis. The micro support has a central upper cavity extending along the vertical axis within the micro support. The micro support has a lower end connected to the substrate layer and an upper end connected to the microstructure for supporting the microstructure with respect to the substrate layer. The micro support is a multilayer micro support comprising two conductive paths and a layer made of dielectric material. The conductive paths and the layer of the micro support extend from the upper end to the lower end thereof. The two conductive paths connect respectively the two first contacts to the two second contacts.

Abstract: An integrated circuit is formed that contains a ferroelectric element comprising metal oxide material containing at least two metals. Various methods and structures are applied to minimize the degradation of ferroelectric properties caused by hydrogen during fabrication of the circuit. Oxygen is added to the some elements of the integrated circuit to serve as a getter of hydrogen during fabrication steps. To minimize hydrogen degradation, the ferroelectric compound can be fabricated from a liquid precursor containing one or more of the constituent metals in excess of the amount corresponding to a stoichiometrically balanced concentration. A hydrogen barrier layer, preferably comprising titanium nitride, is formed to cover the top of the ferroelectric element. A hydrogen heat treatment in hydrogen gas is performed on the integrated circuit at a temperature from 200.degree. to 350.degree. C.

Abstract: A fine semiconductor device having a short channel length while suppressing a short channel effect. Linearly patterned or dot-patterned impurity regions 104 are formed in a channel forming region 103 so as to be generally parallel with the channel direction. The impurity regions 104 are effective in suppressing the short channel effects. More specifically, the impurity regions 104 suppress expansion of a drain-side depletion layer, so that the punch-through phenomenon can be prevented. Further, the impurity regions cause a narrow channel effect, so that reduction in threshold voltage can be lessened.

Abstract: A process for creating a DRAM capacitor structure, comprised of a storage node electrode, featuring an HSG silicon layer, on the surface of the storage node electrode, used to increase capacitor surface area, has been developed. The process features the use of a UHV system, allowing: a pre-clean procedure; an HSG seeding procedure; an anneal procedure used to create an HSG silicon layer; and a silicon nitride deposition; all to be performed in situ, without exposure to air, thus removing, and avoiding, unwanted native oxide layers. This invention allows a nitride--oxide, capacitor dielectric layer, to be formed in situ, in the UHV system, on an underlying storage node electrode structure, which in turn experienced in situ procedures, in the UHV system, resulting in HSG silicon layer, formed after an in situ, pre-clean, an HSG silicon seeding procedure, and an anneal procedure.