Abstract: A semiconductor chip has a nonvolatile memory formed on the upper surface side of a semiconductor substrate. The chip includes at least one recess portion formed in the lower surface of the semiconductor substrate. The recess portion is located in a region corresponding to the nonvolatile memory. A method of manufacturing the semiconductor chip is also disclosed.

Abstract: The semiconductor memory device comprises a field shield element isolation structure for defining a plurality of element regions electrically isolated from one another; a plurality of memory cells disposed in a matrix of rows and columns, each including a transistor having two impurity diffusion layers, a gate electrode and a capacitor; a plurality of bit lines extending in a row direction; a plurality of word lines extending in a column direction; a plurality of memory cell pairs, each formed in one of the element regions and including adjacent two of the memory cells disposed in the row direction, wherein each of the transistors of the two memory cells in each memory cell pair has two impurity diffusion layers, one of which is common to both the transistors and connected to one of the bit lines extending in the row direction immediately thereabove through a first pad polycrystalline silicon film; a second pad polycrystalline silicon film formed on the other impurity diffusion layer of each transistor so as

Abstract: A method of fabricating a bit line on a semiconductor substrate is provided. First, an oxide layer is formed and patterned on the substrate. An epitaxial layer is formed on the exposed substrate after patterning the oxide layer. A first spacer and a second spacer are sequentially formed on the sidewalls of a opening of the oxide layer. A trench is formed by partially removing the epitaxial layer and the substrate. A liner oxide layer is formed in the trench after removing the second spacer. A polysilicon layer as a conductive layer is formed in the trench after removing the first spacer. Then, a step of ion implantation and an annealing step are carried out. A buried bit line is formed after etching back the polysilicon layer.

Abstract: The present invention, generally speaking, provides a magnetic memory element that is single domain in nature and has a geometry that mitigates the effects of half-select noise. In a preferred embodiment, the magnetic memory element takes the form of a magnetic post or tube having an aspect ratio in the range of 2:1 (more preferably 4:1). The outside diameter of the magnetic tube or post is preferably less than 0.8 microns, more preferably 0.6 microns or less. The magnetic post or tube then functions as a single magnetic domain. In the case of a magnetic tube, the skin of the tube is formed of a magnetic material and the interior of the tube is formed of a non-magnetic material. Suitable non-magnetic materials include copper, gold and silicon. The coercivity of the magnetic tube structure may be adjusted by adjusting the thickness of the magnetic skin. As a result, the magnetic memory element is readily scalable to smaller geometries as lithographic techniques improve.

Abstract: A gallium nitride semiconductor layer is fabricated by masking an underlying gallium nitride layer with a mask that includes an array of openings therein, and growing the underlying gallium nitride layer through the array of openings and onto the mask, to thereby form an overgrown gallium nitride semiconductor layer. Although dislocation defects may propagate vertically from the underlying gallium nitride layer to the grown gallium nitride layer through the mask openings, the overgrown gallium nitride layer is relatively defect free. The overgrown gallium nitride semiconductor layer may be overgrown until the overgrown gallium nitride layer coalesces on the mask, to form a continuous overgrown monocrystalline gallium nitride semiconductor layer. The gallium nitride semiconductor layer may be grown using metalorganic vapor phase epitaxy. Microelectronic devices may be formed in the overgrown gallium nitride semiconductor layer.

Abstract: A method for assessing alterations in the dielectric properties of insulating layers on a wafer of semiconductor material induced by plasma treatments. The method includes forming cells of EEPROM type on a wafer with source, drain and control gate surface terminals (pads), subjecting the cells to UV radiation so as to erase them thereby fixing a reference threshold voltage, applying programming voltages of preset value to at least one of the cells and measuring the corresponding threshold voltages, and subjecting this cell to UV radiation so as to restore its threshold to the reference value. The wafer is then subjected to the plasma treatment to be assessed, and the threshold voltages of the cells are measured and compared with the reference threshold voltage so as to derive from the comparison information on the alterations induced on the dielectrics formed on the wafer and on the distribution of the plasma potential.

Abstract: A semiconductor distortion sensor comprises a flexible cantilever having a free end portion and a fixed end portion. A p-type region and an n-type region define a pn junction formed in a preselected region of the cantilever where stress-caused distortion occurs due to flexure of the cantilever upon displacement of the free end portion of the cantilever. When the free end portion of the cantilever is subjected to displacement, the cantilever is flexed and the amount of displacement of the free end portion of the cantilever is detected on the basis of a change in an electrical characteristic of the pn junction.

Abstract: Methods of forming bipolar junction transistors having preferred base electrode extensions include the steps of forming a base electrode of second conductivity type (e.g., P-type) on a face of a substrate. A conductive base electrode extension layer is then formed in contact with a sidewall of the base electrode. The base electrode extension layer may be doped or undoped. An electrically insulating base electrode spacer is then formed on the conductive base electrode extension layer, opposite the sidewall of the base electrode. The conductive base electrode extension layer is then etched to define a L-shaped base electrode extension, using the base electrode spacer as an etching mask. Dopants of second conductivity type are then diffused from the base electrode, through the base electrode extension and into the substrate to define an extrinsic base region therein.

Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.

Abstract: A solid-state image pick-up device having a structure in which the amount of transferred charges is not reduced in a vertical CCD portion even if a pixel portion is made finer, and a method for manufacturing the solid-state image pick-up device are provided. A first p-type well and a second p-type well are formed on an N (100) silicon substrate. A vertical CCD n.sup.+ layer is formed in the second p-type well 3. Then, impurity ions are implanted into a surface layer of the N (100) silicon substrate including an upper layer portion of the vertical CCD n.sup.+ layer to form a p.sup.- layer. An isolating portion for isolating photodiode portions from the vertical CCD n.sup.+ layer and a read control portion for controlling the read of charges from the photodiode n layer are simultaneously formed on a portion adjacent to the vertical CCD n.sup.+ layer.

Abstract: A micromechanical device contains, on a carrier or substrate (1, 10), a micromechanical region which is covered on the chip by a planar covering (D) arranged on the carrier. A method for the production of a micromechanical device of this type provides that a body is formed in which a first insulating layer (2, 11) is arranged on a carrier (1, 10) and a silicon layer (3, 12) is arranged over the insulating layer. The silicon layer (3, 12) is structured, openings (L, LS) being formed down to the first insulating layers. An insulating layer region (IS, 13) and a planar further layer (P, 14) are applied. The further layer (P, 14) is structured, openings being formed down to the insulating layer region (IS, 13). The insulating layer region and the regions of the first insulating layer which are situated underneath it are selectively etched, and a covering layer is applied over the further layer as a planar covering (D). The device can be mounted in a plastic housing without a clean room atmosphere.

Abstract: A charge coupled device is disclosed including: a well formed in a substrate, the well having a conductivity opposite to that of the substrate; a first conductivity type of BCCD region formed on the well; a first lightly doped impurity region formed in a predetermined portion of the first conductivity type of BCCD region; a heavily doped impurity region formed in a predetermined portion of the BCCD region, the heavily doped impurity region having a predetermined distance from the first lightly doped impurity region; a second lightly doped impurity region formed between the first lightly doped impurity region and heavily doped impurity region; a first polysilicon gate formed over a portion of the BCCD region, placed between the first lightly doped impurity region and heavily doped impurity region; and a second polysilicon gate formed over the first lightly doped impurity region. The realization of high speed CCD and simplification of the circuit configuration can be obtained by using one-phase clocking.

Abstract: This invention is a test methodology that immediately retests failed chips to recover false tester reads with no loss of test floor capacity during multiprobe production testing of integrated circuit chips on a wafer. This method retests a chip a second time prior to the multiprobe going to the next chip on the wafer, thus eliminating lost time in repositioning the multiprobe.

Abstract: An A1 pad (11) is provided on a field oxide film isolation (5). The A1 pad (11) is electrically connected to a gate electrode (7) with an A1 wiring pattern (10) and the like. In measurement, a probe (3) comes into contact with the A1 pad (11) to apply a voltage thereto. The probe (3) does not come into direct contact with the gate electrode (7), and therefore no stress is applied to a region below a gate insulation film (6) in which a depletion layer is to be created. With this structure, more accurate result is obtained in a test of estimating defects at an isolation edge using a C-t measurement method.

Abstract: An SOI semiconductor substrate of a semiconductor device includes an SOI layer, an embedded oxide film, a semiconductor substrate, an insulating layer, and a protective coat. The protective coat protects the insulating layer from an oxide film etchant in semiconductor manufacturing processes. The stress applied between the semiconductor substrate, embedded oxide film, and insulating layer is relaxed and restrained.

Abstract: A structure of metal contact portion of a semiconductor device, includes a semiconductor substrate having an impurity doped junction therein, an insulating layer pattern formed on the semiconductor substrate having a contact hole through the insulating layer pattern to expose the doped junction, a conductive projection formed directly on a portion of the doped junction, and a metal layer formed on opposite sides of the conductive projection and contacting the doped junction and the conductive projection, whereby a contact area for the doped junction is increased.

Abstract: The invention is a method and resulting device which provides a strong bond between a silicon substrate and an oxide component mounted within a cavity in the substrate. A layer of titanium, for example, is deposited on the walls of the cavity, followed by deposition of a layer of aluminum. The structure is preferably annealed to form titanium silicide and titanium-aluminum interface layers. The component is then bonded to the aluminum layer.

Abstract: After a TiN film is formed on an Si substrate by sputtering, CVD or the like, an optical constant such as a refractive index of the TiN film is measured. If the refractive index relative to light having a wavelength of 700 nm is 2.0 or smaller, it is judged that a nitridation degree of the TiN film is sufficiently high (near to a composition ratio Ti/N=1). A W film formed on the TiN film judged as above has good adhesion relative to the TiN film. This W film forming method may be applied to forming a wiring with a W plug.

Abstract: A semiconductor package and semiconductor device are provided which enable manufacturing of same with ease of inspection, good reliability, and good thermal characteristics. An insulator made of an organic material and a wiring pattern formed by a metallic foil are formed on top of a metallic base substrate, thereby forming a laminated structure. The metallic base substrate has a plurality of electrically insulated continuity checking terminals. The metallic base substrate, the continuity checking terminals, and the wiring pattern are connected by via holes which pass through the insulator at prescribed locations. The insulator and wiring pattern is removed at a prescribed location at which a semiconductor chip is to be mounted. The exposed metallic base substrate is formed as a cavity of a prescribed depth.

Abstract: The integrated circuits array with latch up protection includes an active array and a guard array. The active array contains a plurality of integrated circuits devices having operational functions. The guard array abutting an outer peripheral portion of the active array contains a plurality of transistors for protecting the plurality of integrated circuits devices from latch up. In general, the active array can be functional circuits like a memory array or a read only memory (ROM) array. The plurality of transistors in the guard array can be formed simultaneously with transistors in the active array and have same structure with the transistors.