Abstract: A test structure used to measure metal bottom coverage in semiconductor integrated circuits. The metal is deposited in etched trenches, vias and/or contacts created during the integrated circuit manufacturing process. A predetermined pattern of probe contacts are disposed about the semiconductor wafer. Metal deposited in the etched areas is heated to partially react with the underlying and surrounding undoped material. The remaining unreacted metal layer is then removed, and an electrical current is applied to the probe contacts. The resistance of the reacted portion of metal and undoped material is measured to determine metal bottom coverage. Some undoped material may also be removed to measure metal sidewall coverage. The predetermined pattern of probe contacts is preferably arranged in a Kelvin or Vander Paaw structure.

Abstract: An electronics module consists generally of a refractory metal sheet coated with a refractory insulator film which in turn is coated with a film of silicon within which thin film transistor electronics circuits are further generated along with interconnection means. Particulate matter is deposited in a desired pattern by a printing process and then fused into smooth thin films by means of an infrared laser. Insulator particles are first deposited onto the refractory metal sheet and then melted and fused into a smooth film adhered to the metal sheet. Silicon particles are next deposited on the insulator film and melted and crystallized into electronic quality silicon film. TFT electronics are next generated in the silicon by well-known means. A plurality of individual modules can be disposed in patches over an extended area both conserving material and providing mechanical flexibility as required by certain applications.

Abstract: A method used during the formation of a semiconductor device comprises the steps of forming a polycrystalline silicon layer over a semiconductor substrate assembly and forming a silicon nitride layer over the polycrystalline silicon layer. A silicon dioxide layer is formed over the silicon nitride layer and the silicon dioxide and silicon nitride layers are patterned using a patterned mask having a width, thereby forming sidewalls in the two layers. The nitride and oxide layers are subjected to an oxygen plasma which treats the sidewalls and leaves a portion of the silicon nitride layer between the sidewalls untreated. The silicon dioxide and the untreated portion of the silicon nitride layer are removed thereby resulting in pillars of treated silicon nitride. Finally, the polycrystalline silicon is etched using the pillars as a mask. The patterned polycrystalline silicon layer thereby comprises features having widths narrower than the width of the original mask.

Abstract: In a nitride compound semiconductor light emitting device, an In.sub.0.3 Ga.sub.0.7 N/GaN multi-quantum well active layer 105 or an In.sub.0.1 Ga.sub.0.9 N/GaN multi-quantum well adjacent layer 104 is made as a saturable absorptive region so that self-pulsation occurs there. Thus, the device ensures self-pulsation with a high probability with a simple structure, and satisfies requirements for use as an optical head for reading data from an optical disc.

Abstract: The fabrication of a resistor structure is described. A resistive region is formed over the top of a substrate. Trenches are formed from the top side of the substrate in scribe line regions where the wafer is to be separated to form resistor modules. Contact layers are formed over the top side of the substrate and are electrically coupled to each end of the resistive region, respectively. The contact layers are also formed over the sidewalls of the trenches. The wafer is separated through the trenches, creating resistor modules having sidewall contact regions.

Abstract: A method of measuring the two-dimensional dopant concentration profile in a source/drain region included in a semiconductor device is disclosed. A semiconductor substrate is etched by an etchant of the kind etching a semiconductor by an amount dependent on a dopant concentration. The etched configuration of the substrate is filled with a filler, and then the filler is separated from the substrate and has its configuration measured. Dopant concentrations and therefore a dopant profile is produced from the configuration of the filler, or a replica of the substrate, measured on the basis of data representative of a relation between the dopant configuration and the amount of etching prepared beforehand. The method insures reliable measurement even in a high dopant concentration region.

Abstract: A rate-of-rotation sensor includes a three-layer system. The rate-of-rotation sensor and the conductor traces are patterned out of the third layer. The conductor traces are electrically insulated (isolated) by cutouts from other regions of the third layer and by a second electrically insulating layer from a first layer. Thus, a simple electrical contacting (configuration) is achieved that is patterned out of a three-layer system. Since the same etching process is used for the first and the third layer, an especially efficient manufacturing is possible.

Abstract: In a CMOS circuit, impurity regions are formed in the channel forming region of each of an n-channel and p-channel transistors along the channel direction. The intervals between the impurity regions in the n-channel transistor is set narrower than those between the impurity regions in the p-channel transistor so as to make the absolute values of the threshold voltages of the n-channel and p-channel transistors approximately equal to each other. Where active layers are formed by utilizing a crystal structural body that is a collection of needle-like or columnar crystals, the same effect can be attained by controlling the width of the needle-like or columnar crystals.

Abstract: The present invention advantageously provides a method for determining lithographic misalignment of a conductive element relative to a via. An electrically measured test structure is provided which is designed to have targeted via areas shifted from midlines of corresponding targeted conductor areas. Further, the test structure is designed to have a test pad that electrically communicates with the targeted via areas. Design specifications of the test structure require the midlines of the conductor areas to be offset from the via areas by varying distances. The above-mentioned method involves processing the designed test structure. An electrical signal may then be applied to each of the conductors while it is also being applied to the test pad. The resulting electrical response should be proportional to the distance that a conductor is misaligned from its desired location. Using the electrical responses for all the conductors, it is possible to determine the direction and amount of misalignment.

Abstract: A display apparatus having electroluminescense (EL) elements includes a light emitting layer for generating light. A high energy laser beam is irradiated on the luminous elemenent layer to define a plurality of regions of the light emitting layer. A plurality of first electrodes are arranged generally parallel to each other over a first surface of the light emitting layer and a plurality of second electrodes are arranged generally parallel to one another and perpendicular to the first electrodes on a second, opposite surface of the light emitting. The EL elements are formed at the intersections of the first and second electrodes.

Abstract: A DRAM cell transistor formed on a silicon substrate comprises a first BPSG film, a silicon oxide film as a supporting film laid thereover, a storage node including a contact portion filling a contact hole extended through the silicon oxide film and the first BPSG film, an oxidized silicon nitride film as a capacitor insulating film, and a plate electrode. There may be further provided a second BPSG film thereover. Even if the first BPSG film at a lower level is caused to reflow by a process for oxidizing the silicon nitride film for formation of the oxidized silicon nitride film as the capacitor insulating film or a process for ref lowing the second BPSG film, the silicon oxide film as the supporting film applies to the capacitor insulating film a stress against the deformation thereof and hence, the oxidized silicon nitride film free from wrinkle or cracks is provided as the capacitor insulating film.

Abstract: A test device for testing an integrated circuit fabricated according to a process is disclosed. The device includes a layout structure, and a excitation circuit. The layout structure includes a plurality of branch structures which are arranged in parallel. Each branch structure includes a feature having a predetermined dimension. The dimension of the feature between associated with adjacent branch structures increases/decreases so as to cover an entire, predetermined spectrum or range of predetermined minimum dimensions. The feature is present (i.e., formed) in a respective branch structure when the process bias/resolution supports fabrication of that dimension. Otherwise, that feature is absent. The excitation circuit is adapted to provide a current through each branch structure to the extent the feature in the branch structure is present. All the branch currents are collected at a common node. If the feature is absent, the current will not be carried, and will thus not contribute to the total current.

Abstract: An optoelectronic device, such as a laser of the ridge waveguide type, can be provided with the necessary mesa (14) by means of wet or dry etching with a mask (20). The etching process is stopped when an etching stopper layer (5) is reached. A laser obtained by wet etching is indeed least expensive, but it is found to have a kink in its power-current characteristic at an undesirably low power value.According to the invention, such a laser must be manufactured in that the mask (20) used is given a width which is (much) greater than the width desired for the mesa (14), and in that, after a (preferably wet) etching process down to or down to close to the etching stopper layer (5), etching is continued with a wet isotropic etchant which is selective relative to the etching stopper layer (5) until the mesa (14) formed has the desired width.A very narrow and steep mesa (14) can thus be realized in an inexpensive manner.

Abstract: The present invention includes forming a first conductive layer on a semiconductor substrate, and forming a first dielectric layer on the first conductive layer. After patterning to etch the first dielectric layer and the first conductive layer, a second dielectric layer is formed on the semiconductor substrate and the first dielectric layer. Next, the second dielectric layer is anisotropically etched back to form a spacer on sidewalls of the first dielectric layer and the first conductive layer. A first silicon oxide layer is then formed over the semiconductor substrate, the first dielectric layer, and the spacer, followed by forming a photoresist layer on the first silicon oxide layer. A predetermined thickness of the first silicon oxide layer is removed by using the photoresist layer as a mask, and a polymer layer is then formed on the photoresist layer and the first silicon oxide layer.

Abstract: A semiconductor device on a semiconductor wafer and the devices made by the method, wherein improvements are realized to agglomeration control, resistivity, and thermal stability of a titanium disilicide layer on a polysilicon layer. Agglomeration control is achieved through the use of two carefully selected low dose barrier diffusion matrix implants into the polysilicon layer, one of which is situated at an interface between the layer of polysilicon and the resultant layer of titanium disilicide film after heat treatment, and the other of which is near the surface of the resultant layer of titanium disilicide film after heat treatment.

Abstract: A method of fabricating a transistor, comprising the following steps. A silicon semiconductor substrate having a pad oxide portion within an active area is provided. A polysilicon layer is deposited over the silicon semiconductor substrate and over the pad oxide portion. A pad oxide layer is deposited over the polysilicon layer. Shallow isolation trench regions are formed on either side of the active area. The pad oxide layer is removed. The polysilicon layer is etched and removed over the pad oxide portion leaving polysilicon portions between the pad oxide portion and the shallow isolation trench regions. The pad oxide portion is replaced with a gate oxide portion. A gate conductor, having exposed side walls, is formed over the gate oxide portion and between the polysilicon portions. Sidewall spacers are formed on the exposed side walls of the gate conductor with the sidewall spacers contacting the polysilicon portions.

Abstract: In manufacturing a CVD film (interlayer insulating film or passivation film) using material gases containing a gas having Si--H combination, the amount of Si--H combination in the CVD film (12, 31, 32, 33, 34, 47, 48, 49, 57, 59) is set to 0.6.times.10.sup.21 cm.sup.-3 or less to thereby suppress the formation of electron traps in the gate oxide film or tunnel oxide film and prevent variations in the threshold of transistors. In addition, the moisture resistance can be improved by setting the refractive index of the CVD film to 1.65 or more or by setting the concentration of nitrogen in the CVD film to 3.times.10.sup.21 cm.sup.-3 or more.

Abstract: The present invention provides a method for forming self-aligned spacers on the horizontal surfaces while removing spacer material from the vertical surfaces. The preferred method uses a resist that can be made insoluble to developer by the use of an implant. By conformally depositing the resist over a substrate having both vertical and horizontal surfaces, implanting the resist, and developing the resist, the resist is removed from the vertical surfaces while remaining on the horizontal surfaces. Thus, a self-aligned spacer is formed on the horizontal surfaces while the spacer material is removed from the vertical surfaces. This horizontal-surface spacer can then be used in further fabrication. The preferred method can be used in many different processes where there is exists a need to differentially process the vertical and horizontal surfaces of a substrate.

Abstract: A method and structure for customizing or repairing integrated circuits using passivated tungsten fuses and low-power energy beams to select which tungsten fuses are to be removed. The tungsten fuses are formed in an array to connect possible connection points of the device. A low-power energy source then selects undesired connection points, and a conventional etch removes the selected tungsten fuses, thereby customizing or repairing the integrated circuit. Because neither precision custom masks nor high energy laser sources are required, the problems associated with conventional methods are reduced or eliminated.

Abstract: An integrated circuit gate array structure includes: a semiconductor substrate including a plurality of columns of semiconductor material of a first conductivity type and a plurality of columns of semiconductor material of a second conductivity type; active areas formed within the columns to which can be connected conductive material, thereby forming active regions; gate connection regions, each controlling a flow of current between a source and a drain which are formed in each of the active regions, wherein each gate connection region has single gate connection pad region; and tap regions formed outside the columns, each of the tap regions being associated with one pair of the columns, the tap region being dropped with an opposite material than their respective columns thereby allowing current and voltage characteristics of the columns to be controlled.